诚聘 ASIC Verification Engineer

asic_tapeout

诚聘 ASIC Verification Engineer [复制链接]

美资公司LSI上海研发中心高薪诚聘通讯存储领域人才，薪水待遇优厚，今年开始配股了，部分人员有出国培训机会。(部门内部推荐,成功机会更高)
有意者请将中英文简历发送至：asic_tapeout@hotmail.com
ASIC Verification Engineer
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
As a member of the Read Channel team, candidate must be willing to work as an extended
member of the design team. Duties will include functional verification of Storage read
channel mixed-signal IP. Candidate will be expected to contribute to design and development
of System Verilog based verification environment and will be responsible for verification
closure of block/chip/system level functions for mixed signal based IP. Experience with
System Verilog and functional coverage methodologies are required. Must be willing to
follow a disciplined verification methodology and to work closely with a multi-location,
international design team. Excellent teamwork and communication skills are required.
PREFERRED EXPERIENCE:
BSEE with 3-5+ years of design and/or verification experience required, MSEE preferred.
Required knowledge and skills:
- Expertise in System Verilog required
- Good understanding of Digital Signal Processing
- Good understanding of Analog and Digital Circuits
- Very good analytical/debugging skill
- Good verbal and written communication skills
Desirable skills:
- Knowledge of Verilog-AMS, Perl
- Knowledge of verification methodologies including functional coverage and constrained
random testing
- Knowledge of VLSI design flows & DFT
- Familiarity of high level programming language
- Experience working with globally distributed team

asic_tapeout

美资公司LSI上海研发中心高薪诚聘通讯存储领域人才，薪水待遇优厚，今年开始配股了，部分人员有出国培训机会。(部门内部推荐,成功机会更高)
有意者请将中英文简历发送至：asic_tapeout@hotmail.com

ASIC Customer Engineer
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
The Customer Design Engineer is a challenging and cutting-edge position working with LSI
internal methodology and foundation IP development teams to support complex ASIC designs
for either external tier one customers or internal ASSP programs.
As an integral member of the customer design engineering team, the ASIC Customer Engineer
has responsibility for a wide range of tasks, including chip floor planning, place and route,
timing analysis, signal integrity, test, and design verification.
Responsible for support and completion of designs from customer provided RTL or Gate level
netlist using the latest LSI technologies.
Design completion tasks include
- Presales Support (die size support, memory generation, address customer questions and
concerns.)
- RTL Analysis & Synthesis
- Physical Design Implementation (bonding, floor planning, power structure insertion, place
and route, timing closure) using Synopsys Astro or ICC tools
- Test insertion using Mentor, LogicVision, or Virage tools
- Formal Verification (Verplex or Formality)
- Static Timing Analysis (Primetime and Primetime SI)
- Cross talk analysis
- Power verification
- DRC & LVS
Overtime, all ASIC customer engineers within the design center are expected to develop the
skills to be able to do most of the tasks described above in this role. Candidates having strong
skill sets one or more of the following areas should apply:
RTL Analysis/Synthesis/STA: The ideal candidate should have strong skills for the front-end of
design implementation which includes RTL Analysis, Synthesis Strategies, and STA setup for
complex ASIC environments. This would include strategies for power management.
or
Physical Design Implementation: The ideal candidate should be strong in either the Physical
Design which includes floor planning, design closure, & STA. Having strong DRC & LVS skills
are a plus. Strong Synopsys Astro/ICC experience a plus. Having strong Mentor Calibre skills
a plus.
or
Confidential
DFT: The ideal candidate should be strong in all DFT (Design for Test) for all aspects. This
would include scan/TDF, TestKompress, MEMBIST/BISR, JTAG and etc… Having strong STA
skills is a plus for timing for all aspects of test. Responsible for support / debug of customer
designs after delivery of prototypes
Strong communications skills are important to this position. This is a position for developing
and honing verbal and written communication skills, and for interfacing to many different
people and engineering teams within LSI. Position requires weekly interface with LSI
customers.
A successful candidate will have strong debug skills, good scripting skills, and hands on
experience with physical design and test tools. Previous experience in taping out an ASIC or
ASSP is ideal for this position.
PREFERRED EXPERIENCE:
5+ years experience in ASIC design and implementation. Familiar with Verilog RTL coding,
Verilog Simulators (NC or VCS) , Synopsys Design Compiler, Synopsys ICC Physical design
tools, PrimeTime for Static Timing Analysis, Mentor FastScan, LogicVision, Verplex (or
Formality), and scripting. The ideal candidate should have completed at least one successful
ASIC or ASSP tapeout. Successful tape out using Synopsys Astro or ICC considered a strong
plus. Experience in working with customers desired. Experience in working with and
debugging prototypes considered a strong plus. Knowledge and hands on use of test insertion
/ vector generation / verification a plus. Some experience with Signal integrity a bonus. Must
possess excellent communication skills; be able to effectively communicate with other
members of the design team, supporting organizations, and management.
Education/Certifications
BS/MS Electrical, Computer Engineering or Equivalent.

asic_tapeout

美资公司LSI上海研发中心高薪诚聘通讯存储领域人才，薪水待遇优厚，今年开始配股了，部分人员有出国培训机会。(部门内部推荐,成功机会更高)
有意者请将中英文简历发送至：asic_tapeout@hotmail.com

Analog Mixed Signal Physical Design (Layout) Engineer
Job Description
LSI's Storage Peripherals Group is looking for an experienced IC physical design engineer to join the pre-amplifier design team. As a preamp physical design (layout) engineer you will work closely with circuit design to implement high-speed custom analog designs and develop mask layouts for customer products. You will join a cross-functional team responsible for developing leading edge high-speed magneto electronic read/write IC products that ultimately achieve high volume production
- Layout high speed analog and mixed-signal custom chips for the hard disk drive industry
- Work directly with a team of engineers to determine floor plan, routing and I/O requirements for preamp IC's
- Perform IC design rule and connectivity verification and drive products through mask release flows.
- Contribute to methodology improvements to increase layout and verification efficiency
Requirements/Qualifications (Education)
- Bachelor's degree in Electrical Engineering (or related field) or equivalent experience\Minimum three to five years experience in custom analog IC physical design
- Experience with schematic-driven layout, floor planning, chip level routing, design for manufacturing and design rule and connectivity verification is required
- Experience using Cadence Virtuoso XL and VCAR router preferred
- Familiarity with both analog and digital layout tools and flows, circuit design concepts and IC manufacturing processes desired