如何消除组合电路的毛刺?

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如何消除组合电路的毛刺? [复制链接]

组合电路是不可避免毛刺的,若要消除毛刺可在具体的电路中加个锁存器,不过你的程序本身就不规范,送你一个程序:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY add4_v IS
      PORT(
        sub    :     IN std_logic;
        A, B    :     IN    STD_LOGIC_VECTOR(3 downto 0);
        S    :    OUT    STD_LOGIC_VECTOR(3 downto 0);
        Co  : OUT   STD_LOGIC);
END add4_v;
ARCHITECTURE a OF add4_v IS

    SIGNAL Y,a1,b1 : STD_LOGIC_VECTOR(4 downto 0);
    signal c : std_logic:='0';
  BEGIN
   a1<=c&A;
   b1<=c&B;

PROCESS (sub,A,B)
        BEGIN
         IF sub='0' THEN
            Y<= a1 + b1 ;
         ELSE
            Y<= a1 - b1 ;
         END IF;
        END PROCESS;
   S<=Y(3 downto 0);
   Co<= Y(4);
end a;

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    组合电路怎样加锁存器,消除毛刺? 希望听到你详细的论述