; SRAM Data lines, NOE and NWE configuration
; SRAM Address lines configuration
; NOE and NWE configuration
; NE3 configuration
; NBL0, NBL1 configuration
LDR R0,= 0x44BB44BB
LDR R1,= 0x40011400
STR R0,[R1]
LDR R0,= 0xBBBBB444
LDR R1,= 0x40011404
STR R0,[R1]
LDR R0,= 0xB44444BB
LDR R1,= 0x40011800
STR R0,[R1]
LDR R0,= 0x44444BBB
LDR R1,= 0x40011804
STR R0,[R1]
LDR R0,= 0x44BBBBBB
LDR R1,= 0x40011C00
STR R0,[R1]
LDR R0,= 0xBBBB4444
LDR R1,= 0x40011C04
STR R0,[R1]
LDR R0,= 0x44BBBBBB
LDR R1,= 0x40012000
STR R0,[R1]
LDR R0,= 0x44444B44
LDR R1,= 0x40012004
STR R0,[R1]
; FSMC Configuration
; Enable FSMC Bank1_SRAM Bank