7X256 时钟配置(18.432M晶振) /////////////////////////////////////////////////////////////////////////// // Init PMC Step 2. // Set PLL to 96MHz (96,109MHz) and UDP Clock to 48MHz // PLL Startup time depends on PLL RC filter: worst case is choosen // UDP Clock (48,058MHz) is compliant with the Universal Serial Bus // Specification (+/- 0.25% for full speed) /////////////////////////////////////////////////////////////////////////// AT91C_BASE_PMC->PMC_PLLR = AT91C_CKGR_USBDIV_1 | (16 << 8) | (AT91C_CKGR_MUL & (72 << 16)) | (AT91C_CKGR_DIV & 14); // Wait for PLL stabilization while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) ); // Wait until the master clock is established for the case we already // turn on the PLL while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
/////////////////////////////////////////////////////////////////////////// // Init PMC Step 3. // Selection of Master Clock MCK equal to (Processor Clock PCK) PLL/2=48MHz // The PMC_MCKR register must not be programmed in a single write operation // (see. Product Errata Sheet) /////////////////////////////////////////////////////////////////////////// AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2; // Wait until the master clock is established while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );