crc16 源代码分享

eeleader

crc16 源代码分享 [复制链接]

// Copyright 2007 Altera Corporation. All rights reserved. 
// Altera products are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws. 
//
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design
// License Agreement (either as signed by you or found at www.altera.com).  By
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// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
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// a particular purpose, are specifically disclaimed.  By making this reference
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// other product not provided by Altera.
/////////////////////////////////////////////////////////////////////////////

//// CRC-16 of 8 data bits.  MSB used first.
//   Polynomial 00001021 (MSB excluded)
//     x^12 + x^5 + x^0
//
// Optimal LUT depth 2
//
//        CCCCCCCCCCCCCCCC DDDDDDDD
//        0000000000111111 00000000
//        0123456789012345 01234567
//
// C00  = ........X...X... X...X...
// C01  = .........X...X.. .X...X..
// C02  = ..........X...X. ..X...X.
// C03  = ...........X...X ...X...X
// C04  = ............X... ....X...
// C05  = ........X...XX.. X...XX..
// C06  = .........X...XX. .X...XX.
// C07  = ..........X...XX ..X...XX
// C08  = X..........X...X ...X...X
// C09  = .X..........X... ....X...
// C10  = ..X..........X.. .....X..
// C11  = ...X..........X. ......X.
// C12  = ....X...X...X..X X...X..X
// C13  = .....X...X...X.. .X...X..
// C14  = ......X...X...X. ..X...X.
// C15  = .......X...X...X ...X...X
//
module crc16_dat8 (crc_in,dat_in,crc_out);
input [15:0] crc_in;
input [7:0] dat_in;
output [15:0] crc_out;

wire [15:0] crc_out;

parameter METHOD = 1;

generate
  if (METHOD == 0)
    crc16_dat8_flat cc (.crc_in(crc_in),.dat_in(dat_in),.crc_out(crc_out));
  else
    crc16_dat8_factor cc (.crc_in(crc_in),.dat_in(dat_in),.crc_out(crc_out));
endgenerate

endmodule

////////////////////////////////////////////////////////////////
// Flat version
////////////////////////////////////////////////////////////////

module crc16_dat8_flat (crc_in,dat_in,crc_out);
input [15:0] crc_in;
input [7:0] dat_in;
output [15:0] crc_out;

wire [15:0] crc_out;

wire x7, x6, x5, x4, x3, x2, x1,
       x0, x15, x14, x13, x12, x11, x10, x9,
       x8;

assign crc_out = {x15,x14,x13,x12,x11,x10,x9,x8,x7,x6,x5,x4,x3,x2,x1,
        x0};

wire d0,d1,d2,d3,d4,d5,d6,d7;

assign { d7,d6,d5,d4,d3,d2,d1,d0} = dat_in [7:0];

wire c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,
    c15;

assign { c15,c14,c13,c12,c11,c10,c9,c8,c7,c6,c5,c4,c3,c2,c1,
        c0} = crc_in [15:0];

    xor6 x7i (.out(x7),.a(c10),.b(d6),.c(c14),.d(d2),.e(c15),.f(d7));  // 6 ins 1 outs

    xor6 x6i (.out(x6),.a(c9),.b(d5),.c(c13),.d(d1),.e(c14),.f(d6));  // 6 ins 1 outs

    xor6 x5i (.out(x5),.a(c8),.b(d4),.c(c12),.d(d0),.e(c13),.f(d5));  // 6 ins 1 outs

    xor6 x4i (.out(x4),.a(c12),.b(d4),.c(1'b0),.d(1'b0),.e(1'b0),.f(1'b0));  // 2 ins 1 outs

    xor6 x3i (.out(x3),.a(c11),.b(d7),.c(c15),.d(d3),.e(1'b0),.f(1'b0));  // 4 ins 1 outs

    xor6 x2i (.out(x2),.a(c10),.b(d6),.c(c14),.d(d2),.e(1'b0),.f(1'b0));  // 4 ins 1 outs

    xor6 x1i (.out(x1),.a(c9),.b(d5),.c(c13),.d(d1),.e(1'b0),.f(1'b0));  // 4 ins 1 outs

    xor6 x0i (.out(x0),.a(c8),.b(d4),.c(c12),.d(d0),.e(1'b0),.f(1'b0));  // 4 ins 1 outs

    xor6 x15i (.out(x15),.a(c11),.b(d7),.c(c15),.d(d3),.e(c7),.f(1'b0));  // 5 ins 1 outs

    xor6 x14i (.out(x14),.a(c10),.b(d6),.c(c14),.d(d2),.e(c6),.f(1'b0));  // 5 ins 1 outs

    xor6 x13i (.out(x13),.a(c9),.b(d5),.c(c13),.d(d1),.e(c5),.f(1'b0));  // 5 ins 1 outs

    assign x12 = c8 ^ d4 ^ c12 ^ d0 ^ c15 ^ d7 ^ c4;  // 7 ins 1 outs

    xor6 x11i (.out(x11),.a(c14),.b(d6),.c(c3),.d(1'b0),.e(1'b0),.f(1'b0));  // 3 ins 1 outs

    xor6 x10i (.out(x10),.a(c13),.b(d5),.c(c2),.d(1'b0),.e(1'b0),.f(1'b0));  // 3 ins 1 outs

    xor6 x9i (.out(x9),.a(c12),.b(d4),.c(c1),.d(1'b0),.e(1'b0),.f(1'b0));  // 3 ins 1 outs

    xor6 x8i (.out(x8),.a(c11),.b(d7),.c(c15),.d(d3),.e(c0),.f(1'b0));  // 5 ins 1 outs

endmodule

////////////////////////////////////////////////////////////////
// Depth optimal factored version
////////////////////////////////////////////////////////////////

module crc16_dat8_factor (crc_in,dat_in,crc_out);
input [15:0] crc_in;
input [7:0] dat_in;
output [15:0] crc_out;

wire [15:0] crc_out;

wire x19, x18, x17, x16, x7, x6, x5,
       x4, x3, x2, x1, x0, x15, x14, x13,
       x12, x11, x10, x9, x8;

assign crc_out = {x15,x14,x13,x12,x11,x10,x9,x8,x7,x6,x5,x4,x3,x2,x1,
        x0};

wire d0,d1,d2,d3,d4,d5,d6,d7;

assign { d7,d6,d5,d4,d3,d2,d1,d0} = dat_in [7:0];

wire c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,
    c15;

assign { c15,c14,c13,c12,c11,c10,c9,c8,c7,c6,c5,c4,c3,c2,c1,
        c0} = crc_in [15:0];

    xor6 x19i (.out(x19),.a(c7),.b(c11),.c(c15),.d(d7),.e(d3),.f(1'b0));  // 5 ins 2 outs

    xor6 x18i (.out(x18),.a(c5),.b(d1),.c(c9),.d(c13),.e(d5),.f(1'b0));  // 5 ins 2 outs

    xor6 x17i (.out(x17),.a(c6),.b(c10),.c(d6),.d(c14),.e(d2),.f(1'b0));  // 5 ins 2 outs

    xor6 x16i (.out(x16),.a(c8),.b(d4),.c(c12),.d(d0),.e(1'b0),.f(1'b0));  // 4 ins 2 outs

    xor6 x7i (.out(x7),.a(x17),.b(c6),.c(c15),.d(d7),.e(1'b0),.f(1'b0));  // 4 ins 1 outs

    xor6 x6i (.out(x6),.a(d6),.b(c14),.c(x18),.d(c5),.e(1'b0),.f(1'b0));  // 4 ins 1 outs

    xor6 x5i (.out(x5),.a(x16),.b(c13),.c(d5),.d(1'b0),.e(1'b0),.f(1'b0));  // 3 ins 1 outs

    xor6 x4i (.out(x4),.a(c12),.b(d4),.c(1'b0),.d(1'b0),.e(1'b0),.f(1'b0));  // 2 ins 1 outs

    xor6 x3i (.out(x3),.a(c11),.b(d7),.c(c15),.d(d3),.e(1'b0),.f(1'b0));  // 4 ins 1 outs

    xor6 x2i (.out(x2),.a(c10),.b(d6),.c(c14),.d(d2),.e(1'b0),.f(1'b0));  // 4 ins 1 outs

    xor6 x1i (.out(x1),.a(c9),.b(d5),.c(c13),.d(d1),.e(1'b0),.f(1'b0));  // 4 ins 1 outs

    xor6 x0i (.out(x0),.a(c8),.b(d4),.c(c12),.d(d0),.e(1'b0),.f(1'b0));  // 4 ins 1 outs

    assign x15 = x19;  // 1 ins 1 outs

    assign x14 = x17;  // 1 ins 1 outs

    assign x13 = x18;  // 1 ins 1 outs

    xor6 x12i (.out(x12),.a(x16),.b(c15),.c(d7),.d(c4),.e(1'b0),.f(1'b0));  // 4 ins 1 outs

    xor6 x11i (.out(x11),.a(c14),.b(d6),.c(c3),.d(1'b0),.e(1'b0),.f(1'b0));  // 3 ins 1 outs

    xor6 x10i (.out(x10),.a(c13),.b(d5),.c(c2),.d(1'b0),.e(1'b0),.f(1'b0));  // 3 ins 1 outs

    xor6 x9i (.out(x9),.a(c12),.b(d4),.c(c1),.d(1'b0),.e(1'b0),.f(1'b0));  // 3 ins 1 outs

    xor6 x8i (.out(x8),.a(x19),.b(c7),.c(c0),.d(1'b0),.e(1'b0),.f(1'b0));  // 3 ins 1 outs

endmodule

eeleader-mcu

写的太复杂，看不懂，我贡献一个我自己写的经过验证的CRC 程序源代码

--顶层模块：Crc_Gen.Vhd--------------------------------------------------------------------------------
--模块名称：Crc_Gen-----------------------------------------------------------------------------
--模块功能：对输入的数据进行CRC校验，校验等式X15+X13+1--------------------------------------------------
--模块说明：输入数据有效，通过Data_En 高脉冲(宽度一个系统时钟脉冲);输出数据，通过Crc_Rdy高脉冲(宽度一个系统时钟脉冲)
--          参数说明：D_Width表示输入数据的位数，Byte_Num：表示输入数据的字节数
--修改记录：无
---**************************************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Crc_Gen IS
 GENERIC (D_Width: POSITIVE:=8;Byte_Num:POSITIVE:=8;Module_En:STRING:="Enable");
 PORT
         (
            Clk  : IN STD_LOGIC;
            Rst  : IN STD_LOGIC;
            Data_In: IN STD_LOGIC_VECTOR (D_Width-1 DOWNTO 0);
            Data_En: IN STD_LOGIC;
            Crc_Out: OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
            Crc_Rdy: OUT STD_LOGIC
          );
         
END Crc_Gen;

ARCHITECTURE Arch_Crc_Gen OF Crc_Gen IS
TYPE   Comp_Crc_State_Type IS (Idle,Crc_Comp,Shift);
SIGNAL Comp_Crc_State: Comp_Crc_State_Type;           
SIGNAL Comp_Crc_Data_In_Reg :STD_LOGIC_VECTOR (D_Width-1 DOWNTO 0);

           
BEGIN
Crc_Gen:IF (Module_En="Enable")GENERATE
Comp_Crc: PROCESS (Clk,Rst)
VARIABLE  Comp_Crc_Result:STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE  Comp_Crc_Data_Reg:STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE  Comp_Crc_Flag:STD_LOGIC;
VARIABLE  Comp_Crc_Cnt: INTEGER RANGE 0 TO Byte_Num;
BEGIN
 IF(Rst='1') THEN
    Crc_Out<=(OTHERS=>'0') ;
    Crc_Rdy<='0';
    Comp_Crc_Data_In_Reg<=(OTHERS=>'0');
    Comp_Crc_Result:=(OTHERS=>'1');
    Comp_Crc_Data_Reg:=(OTHERS=>'1');
    Comp_Crc_Flag:='0';
    Comp_Crc_Cnt:=Byte_Num;
    Comp_Crc_State<=Idle;
 ELSIF Clk'EVENT AND Clk='1' THEN
           
       CASE  Comp_Crc_State  IS
   WHEN Idle=>
       Crc_Rdy<='0';
       Comp_Crc_Result:=(OTHERS=>'1');
       IF (Data_En='1') THEN
           Comp_Crc_State<=Crc_Comp;
           Comp_Crc_Data_In_Reg<=Data_In;
       END IF;
   WHEN Crc_Comp=>
       Comp_Crc_Data_Reg:=Comp_Crc_Data_In_Reg(7 DOWNTO 0);
       Comp_Crc_Result:=Comp_Crc_Result XOR Comp_Crc_Data_Reg(7 DOWNTO 0);
       FOR  i IN 0 TO 7 LOOP
       Comp_Crc_Flag:=Comp_Crc_Result(0);
       Comp_Crc_Result:='0'& Comp_Crc_Result(15 DOWNTO 1);
       IF  (Comp_Crc_Flag='1') THEN
       Comp_Crc_Result:=Comp_Crc_Result XOR x"a001";
       END IF;
       END LOOP;
       Comp_Crc_Cnt:=Comp_Crc_Cnt-1;  
       Comp_Crc_State<=Shift;
   WHEN Shift=>
       IF (Comp_Crc_Cnt=0) THEN
           Crc_Rdy<='1';
           Comp_Crc_State<=Idle;
           Crc_Out<=Comp_Crc_Result;
           Comp_Crc_Cnt:=Byte_Num;
       ELSE
           Comp_Crc_State<=Crc_Comp;
           Comp_Crc_Data_In_Reg<=X"00" & Comp_Crc_Data_In_Reg(D_Width-1 DOWNTO 8);
       END IF;
   WHEN OTHERS=>
           Comp_Crc_State<=Idle;
           Crc_Rdy<='0';
   END CASE;
END IF;
END PROCESS Comp_Crc;
END GENERATE Crc_Gen;
END Arch_Crc_Gen;

ssawee

crc算法那么多
这到底是哪个？