always @ (posedge clk) begin R1 <= arth_o; R2 <= data1 & data2; R3 <= data1 + data2; R4 <= R2 + R3; end
上面这段always语句综合后会产生D触发器
always @ (out2, R1, R3, R4) begin out1 <= R1 + R3; out2 <= R3 & R4; out3 <= out2 - R3; end 而这段语句综合的结果只是一个组合逻辑电路。 请问这是什么原因啊?
这个是verilog 语法和综合器决定了。verilog 语法对 posedge clk 这种表达方式都会认为是时钟电路,并且认为是D触发器的时钟,所以
always @ (posedge clk) begin R1 <= arth_o; R2 <= data1 & data2; R3 <= data1 + data2; R4 <= R2 + R3; end
这部分语句综合成D触发器电路;
对于没有 posedge 关键词的敏感信号列表,综合器都把其综合成逻辑电路
always @ (out2, R1, R3, R4) begin out1 <= R1 + R3; out2 <= R3 & R4; out3 <= out2 - R3; end
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