代码如下: module comp1(ina,inb,clk,out1,out2); input ina,inb; input clk; output out1,out2; reg out1,out2; always @(ina,inb) begin if(ina>inb) out1=1; else out1=0; end always @(posedge clk) begin if(ina>inb) out2=1; else out2=0; end endmodule
测试文件: `timescale 1ns/100ps; `include "./comp1.v" module comp1_test; reg clk; reg ina,inb; wire out1,out2; always #120 clk=~clk; //begin // #10 clk=1; //#10 clk=0; // end initial begin clk=0; ina=0; inb=0; #100;ina=0;inb=1; #100;ina=1;inb=0; #100;ina=1;inb=1; #100; end comp1 u1(.ina(ina),.inb(inb),.clk(clk),.out1(out1),.out2(out2)); endmodule
编译的时候提示如下错误:
# Compile of comp1.v was successful. # Compile of comp1_test.v failed with 1 errors. # 2 compiles, 1 failed with 1 error.
错误显示为: can't open `include file "./comp1.v
请问这到底是什么原因啊??谢谢!
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