Computing power going Platinum

安_然

Computing power going Platinum [复制链接]

Introduction
The 80 PLUS? and Climate Savers Computing? initiatives
have set a very aggressive efficiency standard for
puter power supplies. The “Platinum” level of these
standards specifies that puter power supplies must
have an efficiency of 90% at 20% of rated load, 94% at 50%
load, and 91% at 100% load. To meet these standards,
some power-supply designers have chosen to use a phaseshifted,
full-bridge DC/DC converter with synchronous
rectification. This topology is a good choice because it can
achieve zero voltage switching (ZVS) on the primary
FETs. A popular way to drive the synchronous rectifiers is
with signals that are already present driving the primary
FETs. The only problem with doing this is that dead times
on these primary FETs are required to achieve ZVS. This
results in both synchronous rectifiers being off simultaneously
during the freewheeling period, allowing excessive
body-diode conduction and reducing system efficiency.
The purpose of this article is to propose different timing
for driving these synchronous rectifiers to reduce bodydiode
conduction and improve overall system efficiency.
By Michael O’Loughlin
Senior Applications Engineer