新手求助。。达人速度进来赐教啦。。。跪拜。

wangpiaoke

新手求助。。达人速度进来赐教啦。。。跪拜。 [复制链接]

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------
entity signal_gen is
port(clk:in std_logic;
     outp:out std_logic);
end signal_gen;
---------------------------------
architecture bev of signal_gen is
type state is(one,two,three);
signal pre_state1,pre_state2,next_state1,next_state2:state;
signal outp1,outp2:std_logic ;
begin
---------------------------------
process(clk)
begin
if(clk'event and clk='1')then
  pre_state1<=next_state1;
  end if;
end process;
---------------------------------
process(clk)
begin
if(clk'event and clk='0')then
  pre_state2<=next_state2;
end if;
end process;
---------------------------------
process(pre_state1)
begin
case pre_state1 is
  when one=>
  outp1<='0';
  next_state1<=two;
  when two=>
  outp1<='1';
  next_state1<=three;
  when three=>
  outp1<='1';
  next_state1<=one;
end case;
end process;
-----------------------------------
process(pre_state2)
begin
case pre_state2 is
   when one=>
   outp2<='1';
   next_state2<=two;
   when two=>
   outp2<='0';
   next_state2<=three;
   when three=>
   outp<='1';
   next_state2<=one;
end case;
end process;
-------------------------------------
outp<=outp1 and outp2;
end bev;
一个信号发生器，一楼为错误代码。。达人帮忙啊，不知道怎么搞。。哎。。

wangpiaoke

Error (10028): Can't resolve multiple constant drivers for net "outp" at signal_gen.vhd(61)
Error (10029): Constant driver at signal_gen.vhd(46)
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 2 warnings

fengzhang2002

FPGA不是很懂，没时间学

仙猫

　process(pre_state2) 中的最后一个when，应该是给outp2赋值，而不是outp。

wangpiaoke

楼上我爱你，，我太爱你了。。来么么。。。我看了好一会都没看出来。。。是少了个2。。。我真2。。。

drjloveyou

呵呵，写的多了眼就花了，难免滴