verilog assign用法2

eeleader-mcu

verilog assign用法2 [复制链接]

2）module assign_test (

                       clk,

                       lhold,

                       lholda

                   );

 

input clk;

input lhold;

output lholda;

 

reg lholda_r;

      always @(posedge clk)

            if (lhold)

               lholda_r<=lhold;

            else

               lholda_r<=0;

   assign  lholda=lholda_r;

 

endmodule