一个例子,alarm clock,项目有若干个源文件 ,其中有一个后缀为pla的,用modelsim complie all通过了,可加载仿真 的时候提示几个错误:Error: (vsim-3033) F:/hdl_src/mit/tutorial/verilog /CONVERTOR_CKT.v(18): Instantiation of 'CONVERTOR' failed. The design unit was not found. 下面是源文件: CONVERTOR.PLA # .design CONVERTOR .inputnames T0 T1 T2 T3 T4 T5 .outputnames A0 B0 C0 D0 E0 F0 G0 A1 B1 C1 D1 E1 F1 G1 000001 11111100110000 000010 11111101101101 000011 11111101111001 000100 11111100110011 000101 11111101011011 000110 11111100011111 000111 11111101110000 001000 11111101111111 001001 11111101111011 001010 01100001111110 001011 01100000110000 001100 01100001101101 001101 01100001111001 001110 01100000110011 001111 01100001011011 010000 01100000011111 010001 01100001110000 010010 01100001111111 010011 01100001111011 010100 11011011111110 010101 11011010110000 010110 11011011101101 010111 11011011111001 011000 11011010110011 011001 11011011011011 011010 11011010011111 011011 11011011110000 011100 11011011111111 011101 11011011111011 011110 11110011111110 011111 11110010110000 100000 11110011101101 100001 11110011111001 100010 11110010110011 100011 11110011011011 100100 11110010011111 100101 11110011110000 100110 11110011111111 100111 11110011111011 101000 01100111111110 101001 01100110110000 101010 01100111101101 101011 01100111111001 101100 01100110110011 101101 01100111011011 101110 01100110011111 101111 01100111110000 110000 01100111111111 110001 01100111111011 110010 10110111111110 110011 10110110110000 110100 10110111101101 110101 10110111111001 110110 10110110110011 110111 10110111011011 111000 10110110011111 111001 10110111110000 111010 10110111111111 111011 10110111111011 111100 -------------- 111101 -------------- 111110 -------------- 111111 -------------- CONVERTOR_CKT.v module CONVERTOR_CKT ( connect13,disp1,disp2); input [9:0]connect13; output [13:0]disp1, disp2; wire[6:0] connect14 ; CONVERTOR U7 (.T0(1'b0), .T1(1'b0), .T2(connect13[9] ), .T3(connect13[8] ), .T4(connect13[7] ), .T5(connect13[6] ), .A0(connect14[6] ), .B0( connect14[5] ), .C0(connect14[4] ), .D0(connect14[3] ), .E0( connect14[2] ), .F0(connect14[1] ), .G0(connect14[0] ), .A1( disp1[6] ), .B1(disp1[5] ), .C1(disp1[4] ), .D1(disp1[3] ), .E1( disp1[2] ), .F1(disp1[1] ), .G1(disp1[0] ) ); CONVERTOR U8 ( .T0(connect13[5] ), .T1(connect13[4] ), .T2( connect13[3] ), .T3(connect13[2] ), .T4(connect13[1] ), .T5( connect13[0] ), .A0(disp2[13] ), .B0(disp2[12] ), .C0(disp2[11] ), .D0(disp2[10] ), .E0(disp2[9] ), .F0(disp2[8] ), .G0(disp2[7] ), .A1(disp2[6] ), .B1(disp2[5] ), .C1(disp2[4] ), .D1(disp2[3] ), .E1(disp2[2] ), .F1(disp2[1] ), .G1(disp2[0] ) ); HOURS_FILTER U9 ( .TENS_DIGIT_HOURS_IN(connect14), .TENS_DIGIT_HOURS_OUT(disp1[13:7])); endmodule