帮忙解决vhdl：quartus7.2 在运行if..genarate遇到的问题

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帮忙解决vhdl：quartus7.2 在运行if..genarate遇到的问题 [复制链接]

本人在quartus7.2运行如下vhdl代码：
library ieee;

use ieee.std_logic_1164.all;

entity shift is

        generic (len:integer);

  port(a,clk:in std_logic;
  
                     b:out std_logic);
                                 
end shift;

architecture behav of shift is

                component dff
               
                  port(d,clk:in std_logic;
                  
                                          q:out std_logic);
                                                 
            end component;
         
         signal z:std_logic_vector(1 to (len-1));
         
         begin
         
                 g1:for i in 0 to (len-1) generate
                
                         if (i=0) generate
                        
                                 dffx: dff port map(a,clk,z(i+1));
                                
                         end generate;
                        
                         if (i=(len-1)) generate
                        
                                 dffx: dff port map(z(i),clk,b);
                                
                         end generate;                        
                        
                         if (i/=0 and i/=(len-1)) generate
                        
                                 dffx: dff port map(z(i),clk,z(i+1));
                                
                         end generate;                                          
                        
         end generate;
                
end behav;                                                                                                                                             
出现了下面的错误信息：
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
        Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
        Info: Processing started: Sun Oct 05 09:35:59 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shift -c shift
Error (10500): VHDL syntax error at shift.vhd(31) near text "if";  expecting "end", or "(", or an identifier ("if" is a reserved keyword), or "begin", or a concurrent statement
Error (10500): VHDL syntax error at shift.vhd(31) near text "generate";  expecting "<="
Error (10500): VHDL syntax error at shift.vhd(37) near text "if";  expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at shift.vhd(37) near text "generate";  expecting "<="
Error (10500): VHDL syntax error at shift.vhd(41) near text "generate";  expecting ";", or an identifier ("generate" is a reserved keyword), or "architecture"
Error (10500): VHDL syntax error at shift.vhd(43) near text "generate";  expecting "<="
Error (10500): VHDL syntax error at shift.vhd(47) near text "generate";  expecting ";", or an identifier ("generate" is a reserved keyword), or "architecture"
Info: Found 0 design units, including 0 entities, in source file shift.vhd
Warning: Entity "dff" will be ignored because it conflicts with Quartus II primitive name
Info: Found 2 design units, including 1 entities, in source file dff.vhd
        Info: Found design unit 1: dff-rtl
Error: Quartus II Analysis & Synthesis was unsuccessful. 7 errors, 1 warning
        Info: Allocated 153 megabytes of memory during processing
        Error: Processing ended: Sun Oct 05 09:36:00 2008
        Error: Elapsed time: 00:00:01
想问一下vhdl高手，这是怎么回事呢？是quartusii不支持generate语句吗？还是怎么回事呢？上面程序中的dff port(d,clk,q)就是简单的D触发器，兄弟现向大家求助了啊