ＶＨＤＬ计数器问题

zhouzhaofu

ＶＨＤＬ计数器问题 [复制链接]

各位帮忙看下我这个程序　哪有问题？
还有我想在加个输入端口，挡给这个端口１个高电平时计数清零，在给他一个低电平时候　在重新计数
library ieee;
use ieee.std_logic_1164.all;
entity aa is
port (clk,hold : in std_logic;
      ones     : out integer range 9 downto 0;
      tens     : out integer range 2 downto 0);
end aa;
architecture dh of aa is
begin
process (clk)
variable ones : integer range 9 downto 0;
variable tens : integer range 2 downto 0;
begin
if(clk'event and clk='1') then
if hold ='1' then
if (ones = 9) and (tens =2) then
   ones : = 0;
   tens : = 0;
elsif (ones <9) and (tens =2)then
   ones : = ones-1;
elsif (ones =0) and (tens =2)then
   ones : = 0;
   tens : = tens-1;
elsif (ones <9) and (tens =1)then
   ones : = ones-1;
elsif (ones =0) and (tens =1)then
   ones : = 9;
   tens : = tens-1;
elsif (ones <9) and (tens =0)then
   ones : = ones-1;
end if;
end if;
end if;
ones <= ones;
tens <= tens;
end process;
end;

jingdongbo

Error (10500): VHDL syntax error at aa.vhd(17) near text "=";  expecting "(", or an identifier, or a sequential statement,
每个个位上的运算都出现这个错误提示
比如
elsif (ones  <9) and (tens =2)then  
   ones : = ones-1;
elsif (ones =0) and (tens =2)then  
   ones : = 0;中的ones : = ones-1; 和ones : = 0;提示上面的错误

k275868177

我刚才又修改了下程序　
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity aa is
port (clk,hold : in std_logic;
      ones     : out integer range 9 downto 0;
      tens     : out integer range 2 downto 0);
end aa;
architecture dh of aa is
begin
process (clk,hold)
variable ones : integer range 9 downto 0;
variable tens : integer range 2 downto 0;
begin
if(clk'event and clk='1') then
if hold <='1' then
if (ones = 0) and (tens =0) then
ones := 9;
tens := 2;  
elsif (ones <9) and (tens =2)then
  ones := ones-1;
  tens := 2;
elsif (ones =0) and (tens =2)then
ones := 9;
tens := 1;
elsif (ones <9) and (tens =1)then
ones := ones-1;
elsif (ones =0) and (tens =1)then
ones := 9;
tens := 0;
elsif (ones <9) and (tens = 0)then
ones := ones-1;
end if;
end if;
end if;
ones := ones;
tens := tens;
end process;
end;
现在是没有错了　可是老是提示Warning (10034): Output port "ones[3]" at aa.vhd(6) has no driver
　　　　　　　　　　　　　　Warning (10034): Output port "ones[２]" at aa.vhd(6) has no driver
Warning (10034): Output port "ones[１]" at aa.vhd(6) has no driver
Warning (10034): Output port "ones[０]" at aa.vhd(6) has no driver
Warning (10034): Output port "tens[1]" at aa.vhd(7) has no driver
Warning (10034): Output port "tens[０]" at aa.vhd(7) has no driver
Warning: Entity "aa" contains only dangling pins
Warning: Output pins are stuck at VCC or GND
        Warning: Pin "ones[0]" stuck at GND
        Warning: Pin "ones[1]" stuck at GND
        Warning: Pin "ones[2]" stuck at GND
        Warning: Pin "ones[3]" stuck at GND
        Warning: Pin "tens[0]" stuck at GND
        Warning: Pin "tens[1]" stuck at GND
Warning: Design contains 2 input pin(s) that do not drive logic
        Warning: No output dependent on input pin "clk"
        Warning: No output dependent on input pin "hold"
Warning: Following 6 pins have nothing, GND, or VCC driving datain port -- changes to this 　　　　　connectivity may change fitting results
        Info: Pin ones[0] has GND driving its datain port
        Info: Pin ones[1] has GND driving its datain port
        Info: Pin ones[2] has GND driving its datain port
        Info: Pin ones[3] has GND driving its datain port
        Info: Pin tens[0] has GND driving its datain port
        Info: Pin tens[1] has GND driving its datain port
Warning: No paths found for timing analysis

qwertyuhoho

has no driver
说明你的程序中没有对这些端子赋值（do not care）
Output pins are stuck at VCC or GND
说明你程序中某些端口接地或者悬空了（do not care）
Design contains 2 input pin(s) that do not drive logic
说明你没有用到两个端子（do not care）

作简单的调试逻辑的话，这些警告可以忽略

不过看了你的程序
觉得你没有理解std_logic_vector的含义呢

liuhyang

这里揭帖率太低！