#ifdef ENABLE_RCOMP
else if (irq == XLLP_INTC_S_DMEM)
{
// check if the RCOMP interrupt by read DMCISR[RCI] bit.
// if so,
// 1, clear the DMCISR[RCI]
// 2, read the MDCNFG for DMCISR, use the PCODE and NCODE of it to calculate.
// 3, write the PAD_XX with the new value.
XLLP_UINT32_T regIsr;
P_XLLP_DMEM_REGISTER_T pReg = (P_XLLP_DMEM_REGISTER_T) OALPAtoVA(MONAHANS_BASE_REG_PA_DMEMC, FALSE);
XllpINTCEnableSource(irq,XLLP_FALSE);
regIsr = pReg->dmcisr;
if (pReg->dmcisr & XLLP_DMCISR_RCI )
{
OALMSG(OAL_INTR, (L"OALIntrInit: irq number %x\r\n", irq));
pReg->dmcisr &= XLLP_DMCISR_RCI; //all the bits are write-clear bit or read-only bit.
OALMSG(OAL_INTR, (L"OALIntrInit: to update Rcomp()\r\n"));
XllpMemcRcompUpdate( pReg );
}
XllpINTCEnableSource(irq,XLLP_TRUE);
sysIntr = SYSINTR_NOP;
}
#endif
// Board-level interrupts
else
{
UINT32 origIrq = irq; // save the original so we can tell if it's BSP specific irq
if ((irq == IRQ_GPIO0)||(irq == IRQ_GPIO1))
{
// Mask the interrupt
(void) XllpINTCEnableSource(irq,XLLP_FALSE);
#ifdef OAL_BSP_CALLBACKS
// Give BSP chance to translate IRQ -- if there is subordinate
// interrupt controller in BSP it give chance to decode its status
// and change IRQ
irq = BSPIntrActiveIrq(irq);
#endif
} else if(irq == IRQ_GPIOXX_2) {
UINT32 gedr, ggroup, i;
#ifdef BSP_DEBUG_LJ // For Debug - jli@sychip.com.cn
//OALMSG(1, (L"OAL:OEMInterruptHandler: GPIO Irq %d\r\n", irq));
#endif // LJDEBUG
if ((g_pGPIO->gedr0)&0xfffffffc) { // don't care GPIO0 and GPIO1
gedr = g_pGPIO->gedr0;
ggroup = 0;
} else if (g_pGPIO->gedr1) {
gedr = g_pGPIO->gedr1;
ggroup = 1;
} else if (g_pGPIO->gedr2) {
gedr = g_pGPIO->gedr2;
ggroup = 2;
} else if (g_pGPIO->gedr3) {
gedr = g_pGPIO->gedr3;
ggroup = 3;
} else {
//TO-DO: actually, should ASSERT here.
//TEMPORARY FIX: ignore this interrupt to avoid dead loop here
return(SYSINTR_NOP);
}
// Find out which bit causes the IRQ.
i = 0;
while(!(gedr&0x1)) {
gedr = gedr>>1;
i++;
}
i = i + ggroup*32;
//OALMSG(1, (L"OAL:OEMInterruptHandler: i = %d\r\n", i));
// Get current level on that GPIO
//XllpGpioGetLevel (g_pGPIO, i, &(g_GPIOPrevLevel));
// Clear edge detect status first.
// Don't disable edge detect here.
// Otherwise, we may lose GPIO edge interrupt.
// In future, GPIO level interrupt is preferred.
//if (GPIO_RISE&g_GPIOEdgeDetect)
// XllpGpioSetRisingEdgeDetectEnable(g_pGPIO, i, XLLP_OFF);
//if (GPIO_FALL&g_GPIOEdgeDetect)
// XllpGpioSetFallingEdgeDetectEnable(g_pGPIO, i, XLLP_OFF);
XllpGpioClearEdgeDetectStatus (g_pGPIO, i);
// Compose the IRQ number.
irq = IRQ_GPIO_SHARE_BASE - 2 + i;
#ifdef OAL_BSP_CALLBACKS
// Give BSP chance to translate IRQ -- if there is subordinate
// interrupt controller in BSP it give chance to decode its status
// and change IRQ
irq = BSPIntrActiveIrq(irq);
#endif
} else
{
// Mask the interrupt
(void) XllpINTCEnableSource(irq,XLLP_FALSE);
}
// First find if IRQ is claimed by chain
sysIntr = (UINT16)NKCallIntChain((UCHAR)irq);
//fix the Intallable ISR error according to the MS documents.
//If the installable ISR returns SYSINTR_NOP,
//the BSP interrupt handler code will re-enable the interrupt and
//return SYSINTR_NOP.
if (sysIntr == SYSINTR_NOP)
{
//SETREG32(&g_pICReg->icmr, (1 << irq));
(void) XllpINTCEnableSource(irq,XLLP_TRUE);
return SYSINTR_NOP;
}