用quartus编写verilog，一直生成不了状态机

813128 · 发表于2008-11-12 01:23

用quartus编写verilog，一直生成不了状态机 [复制链接]

//整个系统分为读入模块和处理模块
//定义各个端口和变量
module getv8 (vk1,vk0,nk1,nk0,getnum,reset,clk,LD_ON,get_rate,rate,sign,index,state);
input [7:0] vk1,vk0,nk1,nk0;
input getnum,LD_ON,clk,reset;
output reg sign,get_rate;
output reg [15:0] rate;
reg [31:0] temprate;
reg [31:0] sum0_1,sum2_3,sum4_5,sum6_7,sum8_9,sum10_11,sum12_13,sum14_15;
reg [31:0] sum0_3,sum4_7,sum8_11,sum12_15;
reg [31:0] sum0_7,sum8_15;
reg [31:0] sum21;
reg [31:0] sum22;
reg [3:0] cout0_1,cout2_3,cout4_5,cout6_7,cout8_9,cout10_11,cout12_13,cout14_15;
reg [3:0] cout1_0_7;
reg [3:0] cout1_8_15;
reg [3:0] cout0_3,cout4_7,cout8_11,cout12_15;
reg [3:0] cout2_0_7;
reg [3:0] cout2_8_15;
reg [3:0] cout0_7,cout8_15;
reg [3:0] cout3_0_7;
reg [3:0] cout3_8_15;
reg [31:0] WR[15:0];
parameter getdata=3'b000,getsum1=3'b001,getsum2=3'b010,getsum3=3'b011,getsum4=3'b100,sumv=3'b101,getv1=3'b110,getv2=3'b111;
output reg [2:0] state;///////////////////////////////////////////////
output reg [3:0] index;///////////////////////////////////////////////

always @ (posedge clk)
begin
if (reset==0) //初始化
begin
index<=4'b0000;
state<=getdata;
get_rate<=0;
sign<=0;
cout0_1<=4'b0000;
cout2_3<=4'b0000;
cout4_5<=4'b0000;
cout6_7<=4'b0000;
cout8_9<=4'b0000;
cout10_11<=4'b0000;
cout12_13<=4'b0000;
cout14_15<=4'b0000;
cout1_0_7<=4'b0000;
cout1_8_15<=4'b0000;
cout0_3<=4'b0000;
cout4_7<=4'b0000;
cout8_11<=4'b0000;
cout12_15<=4'b0000;
cout2_0_7<=4'b0000;
cout2_8_15<=4'b0000;
cout0_7<=4'b0000;
cout8_15<=4'b0000;
cout3_0_7<=4'b0000;
cout3_8_15<=4'b0000;
end
else
case(state)

/////////////////////////////////////////////////////////////////////////////////////////////////
//起始状态和错误状态
//得到数据
getdata:
begin
get_rate<=0;
//index<=temp;
if(LD_ON==0) //激光器工作
begin
if (getnum==1)
begin
WR[index]<={vk1,vk0,nk1,nk0};//vk整数部分nk小数部分
if (index<15)
begin
index<=index+4'b0001;
state<=getdata;
end

else
begin
index<=index;
state<=getsum1;
end
end

else
begin
index<=index;
state<=getdata;
end
end

else
begin
index<=4'b0000;
state<=getdata;
end
end

///////////////////////////////////////////////////////////////////////////////////////////////////////
//处理数据
getsum1:
begin
{cout0_1,sum0_1}<=WR[0]+WR[1];
{cout2_3,sum2_3}<=WR[2]+WR[3];
{cout4_5,sum4_5}<=WR[4]+WR[5];
{cout6_7,sum6_7}<=WR[6]+WR[7];
{cout8_9,sum8_9}<=WR[8]+WR[9];
{cout10_11,sum10_11}<=WR[10]+WR[11];
{cout12_13,sum12_13}<=WR[12]+WR[13];
{cout14_15,sum14_15}<=WR[14]+WR[15];
state<=getsum2;
end

getsum2:
begin
{cout0_3,sum0_3}<=sum0_1+sum2_3;
{cout4_7,sum4_7}<=sum4_5+sum6_7;
{cout8_11,sum8_11}<=sum8_9+sum10_11;
{cout12_15,sum12_15}<=sum12_13+sum14_15;
cout1_0_7<=cout0_1+cout2_3+cout4_5+cout6_7;
cout1_8_15<=+cout8_9+cout10_11+cout12_13+cout14_15;
state<=getsum3;
end

getsum3:
begin
{cout0_7,sum0_7}<=sum0_3+sum4_7;
{cout8_15,sum8_15}<=sum8_11+sum12_15;
cout2_0_7<=cout1_0_7+cout0_3+cout4_7;
cout2_8_15<=cout1_8_15++cout8_11+cout12_15;
state<=getsum4;
end

getsum4:
begin
cout3_0_7<=cout2_0_7+cout0_7;
cout3_8_15<=cout2_8_15++cout8_15;
state<=sumv;
end

/////////////////////////////////////////////////////////////////////////////////////////////////
//数据输出
sumv:
begin
WR[0]<=WR[1];WR[1]<=WR[2];WR[2]<=WR[3];WR[3]<=WR[4];
WR[4]<=WR[5];WR[5]<=WR[6];WR[6]<=WR[7];WR[7]<=WR[8];
WR[8]<=WR[9];WR[9]<=WR[10];WR[10]<=WR[11];WR[11]<=WR[12];
WR[12]<=WR[13];WR[13]<=WR[14];WR[14]<=WR[15];
//得到的两个和做处理
sum21<={cout3_0_7,sum0_7[31:4]};
sum22<={cout3_8_15,sum8_15[31:4]};
state<=getv1;
end

getv1:
begin
if (sum21>sum22) //比较两个数的大小，前一个大于后一个，sign=1，说明结果为负
begin
sign<=1;
temprate<=sum21-sum22;
end
else //否则，sign=0，说明结果为正
begin
sign<=0;
temprate<=sum22-sum21; //速度等于两个和的差
end
end

getv2:
begin
rate<={sign,temprate[22:8]};
state<=getdata;
get_rate<=1; //Get_rate=1说明可以输出速度
end

/////////////////////////////////////////////////////////////////////////////////////////////////////////
default:
begin
state<=getdata;
index<=4'b0000;
end

//////////////////////////////////////////////////////////////////////////////////////////////////////////
endcase
end
endmodule

corsair0101 · 发表于2008-11-12 22:15

quartus 下生成状态机是有条件限制的，具体查阅期帮助文档，我记得有四五点

乐乐疯狂中 · 发表于2008-11-13 09:19

状态机只是形式而已。完成功能即可，不必强求。

bagege · 发表于2008-11-21 14:57

verilog看起来比较象c一点，嗯得学点

用quartus编写verilog，一直生成不了状态机 [复制链接]

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