关于mealy型状态机

lixin811013

关于mealy型状态机 [复制链接]

module nrz(
    output B_out,
    input B_in,
    input clk,
    input reset_b
    );
reg[1:0]state,next_state;
parameter S_0=0;
parameter S_1=1;
parameter S_2=2;
parameter dont_care_state=2'bx;
parameter dont_care_out=1'bx;

always@(negedge clk or negedge reset_b)
if(reset_b==0)state<=S_0;
else state<=next_state;

always@(state or B_in)begin
B_out=0;
case(state)
S_0:if(B_in==0)next_state=S_1;
    else if(B_in==1)begin next_state=S_2;B_out=1;end
S_1:begin next_state=S_0;B_out=1;end
S_2:begin next_state=S_0;end
default:begin next_state=dont_care_state;B_out=dont_care_out;end
endcase
end

endmodule

为什么报错：
ERROR:HDLCompilers:44 - "nrz.v" line 42 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "nrz.v" line 44 Reference to scalar wire 'B_out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "nrz.v" line 44 Illegal left hand side of blocking assignment

snailsun

我个人认为是数据类型的问题，但是不知道错在哪里，请教各位高手了~

引用楼主 wangjix 的回复:
module nrz(
? ? output B_out,
? ? input B_in,
? ? input clk,
? ? input reset_b
? ? );
reg[1:0]state,next_state;
parameter S_0=0;
parameter S_1=1;
parameter S_2=2;
parameter dont_care_state=2'bx;
parameter dont_care_out=1'bx;

always@(negedge clk or negedge reset_b)
if(reset_b==0)state <=S_0;
else state <=next_state;

always@(state or B_in)begin
B_out=0;
case(state)
S_0:if(B_in==0)next_state=S_1;
? ? else if(B_in==1)begin next_state=S_2;B_out=1;end
S_1:begin next_state=S_0;B_out=1;end
S_2:begin next_state=S_0;end
default:begin next_state=dont_care_state;B_out=dont_care_out;end
endcase
end

endmodule

为什么报错：
ERROR:HDLCompilers:44 - "nrz.v" line 42 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "nrz.v" line 44 Reference to scalar wire 'B_out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "nrz.v" line 44 Illegal left hand side of blocking assignment