求救:RSL10 RAM只能用24KB,剩下的6x8KB怎么用不了?-问题解决
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本帖最后由 xujinxi 于 2021-7-8 19:24 编辑
RSL10规格书中宣称有3x8KB + 6x8KB + 2x8KB,前面的3x8KB + 6x8KB应该可以给M3使用,为什么编译最大只能用到24KB,
多一点就编译报错,超出RAM范围。中间的6x8KB怎样才能使用哦?
规格书:
The data memory used for storing data and intermediate variables of the Arm Cortex-M3 processor, the
LPDSP32, and/or the Bluetooth protocol baseband hardware. This segment of the RSL10 memory map
contains:
• Three 8 KB data RAM instances dedicated to the Arm Cortex-M3 processor
• Six 8 KB data RAM instances accessible to either the LPDSP32 DSP or the Arm Cortex-M3 processor
• Two 8 KB baseband data RAM instances acting as exchange memory between the Bluetooth protocol
baseband hardware and the Arm Cortex-M3 processor
感谢cruelfox和just do两位热心网友,以上问题可以通过如下方法解决。
修改section.ld文档,配置DRAM空间由24KB变为64KB。
/*
MEMORY
{
ROM (r) : ORIGIN = 0x00000000, LENGTH = 4K
FLASH (xrw) : ORIGIN = 0x00100000, LENGTH = 380K
PRAM (xrw) : ORIGIN = 0x00200000, LENGTH = 32K
DRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
DRAM_DSP (xrw) : ORIGIN = 0x20008000, LENGTH = 40K
DRAM_BB (xrw) : ORIGIN = 0x20012000, LENGTH = 16K
}*/
MEMORY
{
ROM (r) : ORIGIN = 0x00000000, LENGTH = 4K
FLASH (xrw) : ORIGIN = 0x00100000, LENGTH = 380K
PRAM (xrw) : ORIGIN = 0x00200000, LENGTH = 32K
DRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
DRAM_DSP (xrw) : ORIGIN = 0x20010000, LENGTH = 8K
DRAM_BB (xrw) : ORIGIN = 0x20012000, LENGTH = 16K
}
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