LEAF_ENTRY StartUp
bl PreInit
;jump directly to OALstartup if this was not a reset
tst r10, #(RCSR_HARD_RESET :OR: RCSR_WDOG_RESET :OR: RCSR_SLEEP_RESET :OR: RCSR_GPIO_RESET)
beq OALStartUp ;----------------------》2
; Initialize the Bulverde memory controller.
bl xlli_mem_init ;-------------------》4
; If we're here because of a hardware reset then skip sleep reset check
tst r10, #RCSR_HARD_RESET
bne Continue_StartUp
; We may be here because of a sleep reset. Try to resume from the sleep
; state. At this point, it may be a watchdog reset or a sleep/software reset.
;
ldr r0, =xlli_PMRCREGS_PHYSICAL_BASE ; read the PSPR register
ldr r0, [r0, #xlli_PSPR_offset] ;
mov r1, r10 ; packed RCSR+PSSR required in r1
bl XllpPmValidateResumeFromSleep ; r0-r6 are lost
cmp r0, #0 ; zero return: OK to restore
bne Failed_Sleep_Resume ; treat as a full-init reset
b Sleep_Reset_Not_SoftReset
Failed_Sleep_Resume
ldr r1, =xlli_RCSR_SMR
bic r10, r10, r1
Continue_StartUp
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; Common startup code.
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...........
? Power-on reset, equivalent to hardware reset, occurs at initial power-on when the power
supply is detected on VCC_BATT.
? Hardware reset results from asserting nRESET, which forces all units into reset state.
? Watchdog reset results from a time-out in the OS timer and can recover control from runaway
code by resetting the processor and peripherals. Watchdog reset is disabled by default and
must be enabled by software. For more information, see Chapter 22, “Operating System
Timers”.
? GPIO reset is a “soft” reset, which preserves some of the registers and real-time clocks.
? Sleep-exit reset provides a reset to modules that have been powered down in sleep or deepsleep
mode so that they can recover properly when powered up to resume normal operation.
2. 有一个复位状态寄存器,用前4个bits表示发生了哪种复位(hw and power-on shared).估计preinit里把这个寄存器读到r10,然后做tst比较。如果这4个bits都是0,那就没有复位发生,不用init,直接startup OAL。