LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY char_ram IS
PORT(address1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END char_ram;
ARCHITECTURE beh_char_ram OF char_ram IS
FUNCTION char_to_integer (indata : CHARACTER) RETURN INTEGER IS
variable result : integer range 0 to 16#39#;
BEGIN
CASE indata IS
WHEN '0' => result := 48;
WHEN '1' => result := 49;
WHEN '2' => result := 50;
WHEN '3' => result := 51;
WHEN '4' => result := 52;
WHEN '5' => result := 53;
WHEN '6' => result := 54;
WHEN '7' => result := 55;
WHEN '8' => result := 56;
WHEN '9' => result := 57;
WHEN OTHERS => result := 48;
END CASE;
RETURN result;
END FUNCTION;
BEGIN
PROCESS(address1)
BEGIN
CASE address1 IS
WHEN "0000" => data1 <= conv_std_logic_vector(char_to_integer('0'),8);
WHEN "0001" => data1 <= conv_std_logic_vector(char_to_integer('1'),8);
WHEN "0010" => data1 <= conv_std_logic_vector(char_to_integer('2'),8);
WHEN "0011" => data1 <= conv_std_logic_vector(char_to_integer('3'),8);
WHEN "0100" => data1 <= conv_std_logic_vector(char_to_integer('4'),8);
WHEN "0101" => data1 <= conv_std_logic_vector(char_to_integer('5'),8);
WHEN "0110" => data1 <= conv_std_logic_vector(char_to_integer('6'),8);
WHEN "0111" => data1 <= conv_std_logic_vector(char_to_integer('7'),8);
WHEN "1000" => data1 <= conv_std_logic_vector(char_to_integer('8'),8);
WHEN "1001" => data1 <= conv_std_logic_vector(char_to_integer('9'),8);
WHEN OTHERS => data1 <= conv_std_logic_vector(char_to_integer('0'),8);
END CASE;
END PROCESS;
END beh_char_ram;
--顶层文件
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LCD_1602 IS
PORT(clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
up: IN STD_LOGIC;
down: IN STD_LOGIC;
LCD_RS : OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
LCD_EN : BUFFER STD_LOGIC;
LCD_DATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END LCD_1602;
SIGNAL state : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL address : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
SIGNAL datain : STD_LOGIC_VECTOR(7 DOWNTO 0);
component char_ram
port( address1 : in std_logic_vector(3 downto 0) ;
data1 : out std_logic_vector(7 downto 0));
end component;
signal clk_int: std_logic;
signal clkcnt: std_logic_vector(15 downto 0);
constant divcnt: std_logic_vector(15 downto 0):="1001110001000000";
signal clkdiv: std_logic;
signal tc_clkcnt: std_logic;
BEGIN
process(clk,reset) --分频
begin
if(reset='0')then
clkcnt<="0000000000000000";
elsif(clk'event and clk='1')then
if(clkcnt=divcnt)then
clkcnt<="0000000000000000";
else
clkcnt<=clkcnt+1;
end if;
end if;
end process;
tc_clkcnt<='1' when clkcnt=divcnt else
'0';
process(tc_clkcnt,reset)
begin
if(reset='0')then
clkdiv<='0';
elsif(tc_clkcnt'event and tc_clkcnt='1')then
clkdiv<=not clkdiv;
end if;
end process;
process(clkdiv,reset)
begin
if(reset='0')then
clk_int<='0';
elsif(clkdiv'event and clkdiv='1')then
clk_int<= not clk_int;
end if;
end process;
process(clkdiv,reset)
begin
if(reset='0')then
LCD_EN <='0';
elsif(clkdiv'event and clkdiv='0')then
LCD_EN <= not LCD_EN;
end if;
end process;
PROCESS(up, down, address) --按增按钮地址加1,按减按钮地址减1,然后将对应该地址的数据输入
BEGIN
IF(up ='0') THEN
address <= address + 1;
ELSIF (down = '0') THEN
IF (address /= "0000") THEN
address <= address - 1;
ELSE
address <= address;
END IF;
END IF;
END PROCESS;
U1: char_ram PORT MAP(address1 => address, data1 => datain);
LCD_DATA <= "00111000" WHEN state = set_ldnf ELSE
"00000110" WHEN state = set_cursor ELSE
"00001111" WHEN state <= set_dcb ELSE
"01000000" WHEN state <= set_ddram ELSE
datain WHEN state <= write_ddram ELSE
"ZZZZZZZZ";
PROCESS(clk_int, reset, state)
BEGIN
if(reset = '0') then
state <= idle;
LCD_RS <= '0';
LCD_RW <= '0';
elsif(clk_int'EVENT AND clk_int = '1') then
LCD_RS <= '0';
LCD_RW <= '0';
-- 主要看下面这段程序,是不是有哪里没有设置呢??
CASE state I
WHEN idle =>
state<=set_ldnf; --功能设置
WHEN set_ldnf =>
state <= set_cursor; --输入设置
WHEN set_cursor =>
state <= set_dcb; --显示设置
WHEN set_dcb =>
state <= set_ddram; --DDRAM地址设置
WHEN set_ddram =>
state <= write_ddram; --写数据
WHEN write_ddram =>
LCD_RS <= '1';
state <= read_ddram; --读数据
WHEN read_ddram =>
state <= idle;
LCD_RW <= '1';