VHDL中arith程序包和除法问题

cclccl985

VHDL中arith程序包和除法问题 [复制链接]

问各位两点问题:
1. 下面vhdl代码中为什么要使用arith程序包呢?
2. msb_sum: INTEGER :=15;
   那么msb_sum /2应该等于7还是等于8呢?为什么?


LIBRARY IEEE;                     --待例化元件
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_unsigned.ALL;
ENTITY addern IS
    PORT (a, b: IN STD_LOGIC_VECTOR;
        result: out STD_LOGIC_VECTOR);
END addern;
ARCHITECTURE behave OF addern IS
  BEGIN
      result <= a + b;
END;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_unsigned.ALL;
ENTITY adders IS
GENERIC(msb_operand: INTEGER := 15; msb_sum: INTEGER :=15);
    PORT(b: IN STD_LOGIC_VECTOR (msb_operand DOWNTO 0);
          result: OUT STD_LOGIC_VECTOR (msb_sum DOWNTO 0));
END adders;
   
ARCHITECTURE behave OF adders IS
       COMPONENT addern
     PORT (   a, b: IN STD_LOGIC_VECTOR;
            result: OUT STD_LOGIC_VECTOR);
    END COMPONENT;  
    SIGNAL a: STD_LOGIC_VECTOR (msb_sum /2 DOWNTO 0);
    SIGNAL twoa: STD_LOGIC_VECTOR (msb_operand DOWNTO 0);
   BEGIN
    twoa <= a & a;
U1: addern PORT MAP (a => twoa, b => b, result => result);
U2: addern  PORT MAP (a=>b(msb_operand downto msb_operand/2 +1),
            b=>b(msb_operand/2 downto 0), result => a);
END behave;