FPGA与DSP通信问题

XuYong虚庸

FPGA与DSP通信问题 [复制链接]

本帖最后由 XuYong虚庸于 2020-6-22 19:37 编辑

各位，本人初次接触FPGA，设计一个图像数据的采集系统。将FPGA采集的数据传给DSP进行处理，DSP用的F28335，所以用的XINTF接口与FPGA相连（如图），FPGA端设计一个异步FIFO，让DSP以DMA方式读取FIFO中的数据。现在仿真得到的时序看，结果写满信号一直为高啊，读使能信号也一直是高，FIFO是不能输出数据的。我的片选信号只是设置为片选7，XRD直接连接到FPGA的。实在不知道问题出在哪里，烦请各位帮忙看看问题所在！先谢过各位！

代码是这样的

#include "DSP2833x_Device.h"    // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File

#define BUF_SIZE 128  // Sample buffer size

#pragma DATA_SECTION(DMABuf1,"DMARAML4");
#pragma DATA_SECTION(DMABuf2,"ZONE7DATA");

volatile Uint16 DMABuf1[BUF_SIZE];
volatile Uint16 DMABuf2[BUF_SIZE];
Uint16 i;

volatile Uint16 *DMADest;
volatile Uint16 *DMASource;

interrupt void xint1_isr(void);
interrupt void xint2_isr(void);
void init_zone7(void);

main(void)
{

// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
InitSysCtrl();

// Step 2. Initialize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio();  // Skipped for this example

// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;

// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
InitPieVectTable();

// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW;       // Allow access to EALLOW protected registers
PieVectTable.XINT1= &xint1_isr;
PieVectTable.XINT2= &xint2_isr;
EDIS; // Disable access to EALLOW protected registers
IER |= M_INT1;                                  //Enable INT1 (1.4 DMA Ch1)
EnableInterrupts();
PieCtrlRegs.PIEIER1.bit.INTx4 = 1;          // 使能PIE组1的INT4
PieCtrlRegs.PIEIER1.bit.INTx5 = 1;          // 使能PIE组1的INT5

//Step 5. User specific code, enable interrupts:
  // Initialize DMA
      DMAInitialize();
init_zone7();

      // Initialize Tables
for (i=0; i<BUF_SIZE; i++)
{
   DMABuf1 = 0;
      DMABuf2 = 0;
}

// Configure DMA Channel
DMADest = &DMABuf1[0];
      DMASource = &DMABuf2[0];
         DMACH1AddrConfig(DMADest,DMASource);
      DMACH1BurstConfig(15,1,1);       //Will set up to use 16-bit datasize, pointers are based on 16-bit words
      DMACH1TransferConfig(15,1,1);    //so need to increment by 1 to grab the correct location
      DMACH1WrapConfig(0xFFFF,0,0xFFFF,0);
      //Use timer0 to start the x-fer.
      //Since this is a static copy use one shot mode, so only one trigger is needed
      //Also using 16-bit mode to decrease x-fer time
DMACH1ModeConfig(DMA_XINT1,PERINT_ENABLE,ONESHOT_ENABLE,CONT_ENABLE,SYNC_DISABLE,SYNC_SRC,OVRFLOW_DISABLE,SIXTEEN_BIT,CHINT_END,CHINT_ENABLE);

//rdreq输出给FIFO
      EALLOW;
      GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3;       // 选择为片选信号
      GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1;       // 方向定义为输出
      EDIS;

//wrfull输入给DSP
      EALLOW;
      GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 0;       // 选择为通用I/O口
      GpioCtrlRegs.GPADIR.bit.GPIO30 = 0;       // 方向定义为输入
      GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 0;       // 外部中断1（XINT1）与系统时钟SYSCLKOUT同步
      EDIS;

//rdempty输入给DSP
      EALLOW;
      GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 0;       // 选择为通用I/O口
      GpioCtrlRegs.GPADIR.bit.GPIO29 = 0;       // 方向定义为输入
      GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 0;       // 外部中断2（XINT1）与系统时钟SYSCLKOUT同步
EDIS;

// 通过GPIO外部中断选择寄存器，选择GPIO30为外部中断1
      EALLOW;
      GpioIntRegs.GPIOXINT1SEL.bit.GPIOSEL = 0x1e; // XINT1是GPIO30
      GpioIntRegs.GPIOXINT2SEL.bit.GPIOSEL = 0x1d; // XINT2是GPIO29
      EDIS;

// 配置外部中断1的中断控制寄存器
      XIntruptRegs.XINT1CR.bit.POLARITY = 1;    // 上升沿触发中断
      XIntruptRegs.XINT2CR.bit.POLARITY = 1;    // 上升沿触发中断

// 使能外部中断1
      XIntruptRegs.XINT1CR.bit.ENABLE = 1;       // 使能XINT1
      XIntruptRegs.XINT2CR.bit.ENABLE = 1;       // 使能XINT2

//步骤6：无限循环
for(;;);

}

//步骤7.在这里插入中断服务子程序，如果需要使用中断服务子程序，必须在步骤5中重新定义中断
//向量表中对应地地址
interrupt void xint1_isr(void)
{
      StartDMACH1();
      GpioDataRegs.GPBSET.bit.GPIO37 = 1;       // 输出高电平,向FIFO发出读信号

      // 应答寄存器的位1清0，以响应同组内其他中断；
      PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

interrupt void xint2_isr(void)
{
      GpioDataRegs.GPBCLEAR.bit.GPIO37 = 1;    // 引脚清0

      // 应答寄存器的位1清0，以响应同组内其他中断；
      PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
void init_zone7(void)
{
      EALLOW;
// Make sure the XINTF clock is enabled
      SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1;
      EDIS;
      // Configure the GPIO for XINTF with a 16-bit data bus
      // This function is in DSP2833x_Xintf.c
      InitXintf16Gpio();

      /*******
      EALLOW;
      GpioDataRegs.GPCSET.bit.GPIO72 = 1;
EDIS;    ********/

// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = SYSCLKOUT/2
      EALLOW;
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
// Buffer up to 3 writes
XintfRegs.XINTCNF2.bit.WRBUFF = 3;
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
// XCLKOUT = XTIMCLK/2
XintfRegs.XINTCNF2.bit.CLKMODE = 1;

// Zone 7------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING7.bit.XWRLEAD = 1;
XintfRegs.XTIMING7.bit.XWRACTIVE = 2;
XintfRegs.XTIMING7.bit.XWRTRAIL = 1;
// Zone read timing
XintfRegs.XTIMING7.bit.XRDLEAD = 1;
XintfRegs.XTIMING7.bit.XRDACTIVE = 3;
XintfRegs.XTIMING7.bit.XRDTRAIL = 0;

// don't double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING7.bit.X2TIMING = 0;

// Zone will not sample XREADY signal
XintfRegs.XTIMING7.bit.USEREADY = 0;
XintfRegs.XTIMING7.bit.READYMODE = 0;

// 1,1 = x16 data bus
// 0,1 = x32 data bus
// other values are reserved
XintfRegs.XTIMING7.bit.XSIZE = 3;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
asm(" RPT #7 || NOP");
}