VHDL写的键盘程序有错误 那位帮解决一下

nearfuture

VHDL写的键盘程序有错误 那位帮解决一下 [复制链接]

library ieee;
        use ieee.std_logic_1164.all;
        use ieee.std_logic_unsigned.all;

entity t is
        port(key0,key1,key2,key3,key4,key5,key6,key7,key8,key9 : in std_logic;
                        clk : in std_logic;
                        key : out integer range 0 to 9);
end;

architecture bhv of t is
begin
        process(key0,key1,key2,key3,key4,key5,key6,key7,key8,key9,clk) --检测按键
        begin
                if clk 'event and clk='1' then
                        if key0 'event and key0='1' then key<=0;
                        elsif key1 'event and key1='1' then key<=1;
                                elsif key2 'event and key2='1' then key<=2;
                                        elsif key3 'event and key3='1' then key<=3;
                                                elsif key4 'event and key4='1' then key<=4;
                                                        elsif key5 'event and key5='1' then key<=5;
                                                                elsif key6 'event and key6='1' then key<=6;
                                                                        elsif key7 'event and key7='1' then key<=7;
                                                                                elsif key8 'event and key8='1' then key<=8;
                                                                                        elsif key9 'event and key9='1' then key<=9;
                        end if;
                end if;
        end process ;
end;       


用quartus II 6.0 编译时显示错误
Error (10001): Verilog HDL or VHDL error at t.vhd(16): can't infer register for key[0] because its behavior depends on the edges of multiple distinct clocks
Error (10001): Verilog HDL or VHDL error at t.vhd(16): can't infer register for key[0] because it does not hold its value outside the clock edge
Error (10001): Verilog HDL or VHDL error at t.vhd(16): can't infer register for key[1] because its behavior depends on the edges of multiple distinct clocks
Error (10001): Verilog HDL or VHDL error at t.vhd(16): can't infer register for key[1] because it does not hold its value outside the clock edge
Error (10001): Verilog HDL or VHDL error at t.vhd(16): can't infer register for key[2] because its behavior depends on the edges of multiple distinct clocks
Error (10001): Verilog HDL or VHDL error at t.vhd(16): can't infer register for key[2] because it does not hold its value outside the clock edge
Error (10001): Verilog HDL or VHDL error at t.vhd(16): can't infer register for key[3] because its behavior depends on the edges of multiple distinct clocks
Error (10001): Verilog HDL or VHDL error at t.vhd(16): can't infer register for key[3] because it does not hold its value outside the clock edge
Error (10001): Verilog HDL or VHDL error at t.vhd(16): couldn't implement registers for assignments on this clock edge
Error (10001): Verilog HDL or VHDL error at t.vhd(17): couldn't implement registers for assignments on this clock edge
Error (10001): Verilog HDL or VHDL error at t.vhd(18): couldn't implement registers for assignments on this clock edge
Error (10001): Verilog HDL or VHDL error at t.vhd(19): couldn't implement registers for assignments on this clock edge
Error (10001): Verilog HDL or VHDL error at t.vhd(20): couldn't implement registers for assignments on this clock edge
Error (10001): Verilog HDL or VHDL error at t.vhd(21): couldn't implement registers for assignments on this clock edge
Error (10001): Verilog HDL or VHDL error at t.vhd(22): couldn't implement registers for assignments on this clock edge
Error (10001): Verilog HDL or VHDL error at t.vhd(23): couldn't implement registers for assignments on this clock edge
Error (10001): Verilog HDL or VHDL error at t.vhd(24): couldn't implement registers for assignments on this clock edge
Error (10001): Verilog HDL or VHDL error at t.vhd(25): couldn't implement registers for assignments on this clock edge
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 19 errors, 0 warnings
        Error: Processing ended: Sat Sep 12 12:44:50 2009
        Error: Elapsed time: 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 19 errors, 0 warnings



哪位高手解决一下

andyzw20

有两个错误
第一个，key输出应该是std_logic_vector(9 downto 0),integer只能作为信号量和变量
第二个，如果要检测按键的边沿应该用2个process，第一个process中temp0 <= key0 ......
第二个process中 if （temp = ‘0’ and key0 = '1'） then key(0) <= '0'
这样就可以检测按键的边沿了

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity keyscan if
    port(
        nrst        : in        std_logic;
        clk        : in        std_logic;
        keyin        : in        std_logic_vector(9 downto 0);
        keyout        : out        std_logic_vector(9 downto 0)
        );
end keyscan;

architecture behav of keyscan if
    signal keytemp : std_logic_vector(9 downto 0);
    begin
        process(nrst,clk)
        begin
            if nrst = '0' then
                keytemp <= (others => '0');
            elsif rising_edge(clk) then
                keytemp <= keyin;
            end if;
        end process;

        process(nrst,clk)
        begin
            if nrst = '0' then
                keyout <= (others => '0');
            elsif rising_edge(clk) then
                if (keytemp(0) = '0' and keyin(0) = '1') then       
                        keyout(0) <= '1';
                elsif (keytemp(1) = '0' and keyin(1) = '1') then
                        keyout(1) <= '1';
                elsif (keytemp(2) = '0' and keyin(2) = '1') then
                        keyout(2) <= '1';
                elsif (keytemp(3) = '0' and keyin(3) = '1') then
                        keyout(3) <= '1';
                elsif (keytemp(4) = '0' and keyin(4) = '1') then
                        keyout(4) <= '1';
                elsif (keytemp(5) = '0' and keyin(5) = '1') then
                        keyout(5) <= '1';
                elsif (keytemp(6) = '0' and keyin(6) = '1') then
                        keyout(6) <= '1';
                elsif (keytemp(7) = '0' and keyin(7) = '1') then
                        keyout(7) <= '1';
                elsif (keytemp(8) = '0' and keyin(8) = '1') then
                        keyout(8) <= '1';
                elsif (keytemp(9) = '0' and keyin(9) = '1') then
                        keyout(9) <= '1';
                end if;
            end if;
        end process;
end behav;

我帮你写了一下，不过没有编译，可能会有一些小错误。
其实键盘扫描的程序比这个要复杂多了，一般都会用到扫描比较滤波存储等模块

jingank

既然是按键了，还用时钟控制干什么？ 把if clk 'event and clk='1' then 时钟沿控制删了，不要用时钟控制的同时再用外部设备控制

3933212440

把所有的if key0 'event and key0='1' 变成if key0 = '1'
不要管key的沿，统统用时钟采样

伊诺洁坡

楼上的在乱讲，把人家正确的写错了。
不要用边缘检测，直接检测key1等的状态

kukuicoco

3楼和5楼说的是对的。
一个proecss只能用一个边沿检测。楼主要注意设计时以硬件的角度去考虑问题，你语法逻辑上是没有问题的，但要知道综合工具是非常"笨的"，但如此语法在综合时工具可能会尝试综合处一个触发器却又很多个输入时钟，显然这在硬件上是无法实现的。

QQWEB

引用 5 楼 liuchaotao 的回复:
楼上的在乱讲，把人家正确的写错了。
不要用边缘检测，直接检测key1等的状态

可以检测边沿的。虽然在一个process中不能实现，但是用2个process是可以的。

mzj116688

我想实现的功能是  如果0～9有键按下  则用key输出