TMS320F28335之GPIO引脚通用输入/输出口

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TMS320F28335之GPIO引脚通用输入/输出口 [复制链接]

 DSP28335 GPIO模块分为三类IO口：PORTA(0-31),PORTB(32-63),PORTC(64-87)
对GPIO模块的设置主要通过三类寄存器来完成，分别是：控制寄存器、数据寄存器、中断寄存器。

1.控制寄存器
  GPxCTRL;    // GPIO x Control Register (GPIO0 to 31)
              //设置采样窗周期T=2*GPXCTRL*Tsysclk；

  GPxQSEL1;   // GPIO x Qualifier Select 1 Register (GPIO0 to 15)(32-47)            
  GPxQSEL2;   // GPIO x Qualifier Select 2 Register (GPIO16 to 31)(48-63)
              //每两位控制一个引脚，确定是3周期采样还是6周期采样或者不用采样

  GPxMUX1;    // GPIO x Mux 1 Register (GPIO0 to 15)(32-47)(64-79)

  GPxMUX2;    // GPIO x Mux 2 Register (GPIO16 to 31)(48-63)(80-95)
              //配置各个引脚的功能，0：I/O功能，1：外设功能。

  GPxDIR;     // GPIO x Direction Register (GPIO0 to 31)(32-63)(64-95)
              //配置每个引脚是输入还是输出，0：数字量输入；1：数字量输出。
  GPxPUD;     // GPIO x Pull Up Disable Register (GPIO0 to 31)(32-63)(64-95)
              //使能或禁止内部上拉 0：开启上拉，1：禁止上拉

2、数据寄存器
  GPxDAT;     // GPIO Data Register (GPIO0 to 31)(32-63)(64-95)
  GPxSET;     // GPIO Data Set Register (GPIO0 to 31)(32-63)(64-95)——置位

  GPxCLEAR;   // GPIO Data Clear Register (GPIO0 to 31)(32-63)(64-95)

  GPxTOGGLE;  // GPIO Data Toggle Register (GPIO0 to 31)(32-63)(64-95)—反转

3、中断寄存器
   GPIOXINT1SEL; // XINT1 GPIO Input Selection
   GPIOXINT2SEL; // XINT2 GPIO Input Selection

   GPIOXNMISEL;  // XNMI_Xint13 GPIO Input Selection

   GPIOXINT3SEL; // XINT3 GPIO Input Selection

   GPIOXINT4SEL; // XINT4 GPIO Input Selection

   GPIOXINT5SEL; // XINT5 GPIO Input Selection

   GPIOXINT6SEL; // XINT6 GPIO Input Selection

   GPIOXINT7SEL; // XINT7 GPIO Input Selection

   GPIOLPMSEL;   // Low power modes GP I/O input select
   可以对GPIO0-63进行外部中断设置；

具体定义在DSP28335Gpio.h中，如下：

struct GPIO_CTRL_REGS {
   union  GPACTRL_REG  GPACTRL;   // GPIO A Control Register (GPIO0 to 31)
   union  GPA1_REG     GPAQSEL1;  // GPIO A Qualifier Select 1 Register (GPIO0 to 15)
   union  GPA2_REG     GPAQSEL2;  // GPIO A Qualifier Select 2 Register (GPIO16 to 31)
   union  GPA1_REG     GPAMUX1;   // GPIO A Mux 1 Register (GPIO0 to 15)
   union  GPA2_REG     GPAMUX2;   // GPIO A Mux 2 Register (GPIO16 to 31)
   union  GPADAT_REG   GPADIR;    // GPIO A Direction Register (GPIO0 to 31)
   union  GPADAT_REG   GPAPUD;    // GPIO A Pull Up Disable Register (GPIO0 to 31)
   Uint32              rsvd1;
   union  GPBCTRL_REG  GPBCTRL;   // GPIO B Control Register (GPIO32 to 63)
   union  GPB1_REG     GPBQSEL1;  // GPIO B Qualifier Select 1 Register (GPIO32 to 47)
   union  GPB2_REG     GPBQSEL2;  // GPIO B Qualifier Select 2 Register (GPIO48 to 63)
   union  GPB1_REG     GPBMUX1;   // GPIO B Mux 1 Register (GPIO32 to 47)
   union  GPB2_REG     GPBMUX2;   // GPIO B Mux 2 Register (GPIO48 to 63)
   union  GPBDAT_REG   GPBDIR;    // GPIO B Direction Register (GPIO32 to 63)
   union  GPBDAT_REG   GPBPUD;    // GPIO B Pull Up Disable Register (GPIO32 to 63)
   Uint16              rsvd2[8];
   union  GPC1_REG     GPCMUX1;   // GPIO C Mux 1 Register (GPIO64 to 79)
   union  GPC2_REG     GPCMUX2;   // GPIO C Mux 2 Register (GPIO80 to 95)
   union  GPCDAT_REG   GPCDIR;    // GPIO C Direction Register (GPIO64 to 95)
   union  GPCDAT_REG   GPCPUD;    // GPIO C Pull Up Disable Register (GPIO64 to 95)
};
 
struct GPIO_DATA_REGS {
   union  GPADAT_REG       GPADAT;       // GPIO Data Register (GPIO0 to 31)
   union  GPADAT_REG       GPASET;       // GPIO Data Set Register (GPIO0 to 31)
   union  GPADAT_REG       GPACLEAR;     // GPIO Data Clear Register (GPIO0 to 31)
   union  GPADAT_REG       GPATOGGLE;    // GPIO Data Toggle Register (GPIO0 to 31) 
   union  GPBDAT_REG       GPBDAT;       // GPIO Data Register (GPIO32 to 63)
   union  GPBDAT_REG       GPBSET;       // GPIO Data Set Register (GPIO32 to 63)
   union  GPBDAT_REG       GPBCLEAR;     // GPIO Data Clear Register (GPIO32 to 63)
   union  GPBDAT_REG       GPBTOGGLE;    // GPIO Data Toggle Register (GPIO32 to 63)
   union  GPCDAT_REG       GPCDAT;       // GPIO Data Register (GPIO64 to 95)
   union  GPCDAT_REG       GPCSET;       // GPIO Data Set Register (GPIO64 to 95)
   union  GPCDAT_REG       GPCCLEAR;     // GPIO Data Clear Register (GPIO64 to 95)
   union  GPCDAT_REG       GPCTOGGLE;    // GPIO Data Toggle Register (GPIO64 to 95)
   Uint16                  rsvd1[8];
};
 
struct GPIO_INT_REGS {
   union  GPIOXINT_REG     GPIOXINT1SEL; // XINT1 GPIO Input Selection
   union  GPIOXINT_REG     GPIOXINT2SEL; // XINT2 GPIO Input Selection
   union  GPIOXINT_REG     GPIOXNMISEL;  // XNMI_Xint13 GPIO Input Selection
   union  GPIOXINT_REG     GPIOXINT3SEL; // XINT3 GPIO Input Selection
   union  GPIOXINT_REG     GPIOXINT4SEL; // XINT4 GPIO Input Selection
   union  GPIOXINT_REG     GPIOXINT5SEL; // XINT5 GPIO Input Selection
   union  GPIOXINT_REG     GPIOXINT6SEL; // XINT6 GPIO Input Selection
   union  GPIOXINT_REG     GPIOXINT7SEL; // XINT7 GPIO Input Selection
   union  GPADAT_REG       GPIOLPMSEL;   // Low power modes GP I/O input select
};