PLC 技术构造综述

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PLC 技术构造综述 [复制链接]

PLC 使用不同的处理技术构建内部的存储器，几乎目前所有流行的PLD都是单极性CMOS-PROCESS，也有极少数的使用双极性 FUSE 技术。基于CMOS-PROCESS 的PLD 可以分成5类，如下图。每种技术可以从上电，可靠性，编程行为比较他们的优缺点。

 

EPROM-technology Erasable Programmable Read-Only Memory EPROM cells are non-volatile memory cells. Similar to the technology used in standard EPROM memory devices. EPROM cells are electrically programmed in a device programmer. EPROM-based devices are erasable using ultra-violet light (UV-light), if they are in a windowed package. EPROM-based devices in a standard package are only one-time programmable (OTP). Typical data retention time : greater than 10 .. 20 years Typical erase/program cycles : OTP .. 10,000 times Typical erase/program times : some minutes UV-light / about 0.1 msec. per cell
EEPROM-technology Electrically-Erasable Programmable Read-Only Memory EEPROM cells are non-volatile memory cells. An EEPROM memory cell is physically larger (about 3 times) than an EPROM cell, but offers the advantage of being erased electrically. Cause of this great advantage many vendors implemented the in-system programmable (ISP) capability . Typical data retention time : greater than 10 .. 20 years Typical erase/program cycles : greater than 1,000 .. 10,000 times Typical erase/program times : some milliseconds per cell / about 0.1 msec. per cell
Flash EPROM-technology Flash Erasable Programmable Read-Only Memory Flash EPROM cells are non-volatile memory cells. FLASH has the electrically-erasable benefits of EEPROM but a smaller physical cell size (about 50%). Most FLASH-based devices are in-system programmable (ISP). Typical data retention time : greater than 10 .. 20 years Typical erase/program cycles : greater than 50 .. 10,000 times Typical erase/program times : about 1 sec. for whole chip / about 0.1 msec. per cell
SRAM-technology Static Random Access Memory Similar to the technology used in static RAM devices, but with a few modifications for maximum stability instead of read/write performance. Because SRAM-technology is volatile (the contents disappear after power-down) the devices have to be bootet (configured) after power-up. This makes the devices in-system programmable (ISP) and reconfigurable during operation mode. Most SRAM-based FPGAs can configure themselves automatically at power-up from an external or internal (on-chip) configuration ROM. Typical data retention time : only at stable power-on (volatile) Typical erase/program cycles : unlimited Typical erase/program times : about some milliseconds / milliseconds .. minutes for whole chip (depends on ROM-interface)
Antifuse-technology Antifuse cells are non-volatile and only one-time programmable (OTP). Instead of breaking a metal connection by passing current through (like fuse-technology), a link is grown to make a connection. Antifuse-based devices are very good for high reliability applications, cause of their unlimited data-retention time. Antifuse cells are electrically programmed in a device programmer. There are different kinds of CMOS-based PLD-Antifuse-technologies known, like PLICE, ViaLink or MicroVia. Typical data retention time : unlimited Typical erase/program cycles : 1 time (OTP) Typical erase/program times : not erasable / some minutes for whole chip (depends on chip complexity)
Fuse-technology Fuse cells are non-volatile and only one-time programmable (OTP). Fuse-technology was the original programming technology for programmable logic. A fuse is a metal link that can be programmed (blown) by passing a current through. Fuse cells are electrically programmed in a device programmer. Typical data retention time : unlimited Typical erase/program cycles : 1 time (OTP) Typical erase/program times : not erasable / some minutes for whole chip (depends on chip complexity)

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