FPGA流水灯设计vhdl源程序

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FPGA流水灯设计vhdl源程序 [复制链接]

1. library ieee;
2. use ieee.std_logic_1164.all;
3. use ieee.std_logic_unsigned .all;
4. entity liushuideng is
5. port(clk:in std_logic;
6. led:out std_logic_vector(7 downto 0));
7. end entity;
8. architecture bhv of liushuideng is
9. signal clk1:std_logic;
10. begin
11. process(clk)
12. variable num:integer range 1 to 25000000;
13. begin 
14. if rising_edge (clk)then 
15. if num=25000000 then num:=1;clk1<=not clk1;
16. else num:=num+1;
17. end if;
18. end if;
19. end process;
20. process(clk1)
21. variable n:integer range 0 to 3;
22. begin
23. if rising_edge (clk1) then
24. if n=3 then n:=0;
25. else n:=n+1;
26. end if ;
27. end if;
28. case n is 
29. when 0=>led<="10001000";
30. when 1=>led<="01000100";
31. when 2=>led<="00100010";
32. when 3=>led<="00010001";
33. when others=>led<="00000000";
34. end case;
35. end process;
36. end bhv;