版主,,这个程序老编译不过去

zhuzhouren

版主,,这个程序老编译不过去 [复制链接]

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY  FRE_DIVE  IS
PORT
   (CLK : IN STD_LOGIC;
    D     : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
    H     : OUT STD_LOGIC
   ）；
END FRE_DIV;

ARCHITECTURE ARCH_FRE_DIV OF FRE_DIV IS
SIGNAL CLK_OUT : STD_LOGIC;
BGEGIN

PROCESS(CLK)
BEGIN
  IF (D=X"FF") THEN
   H<=CLK;
  ELSE
   H<=CLK_OUT;
  END IF;
END PROCESS;

PROCESS(CLK)
VARIABLE CNT,CNT1 : INTEGER RANGE 0 TO 200;
BEGIN
IF CLK'EVENT AND CLK='1' THEN
   IF (D=X"FE") THEN
       CNT1:=2;
   ELSIF (D=X"FD") THEN
       CNT1:=4;
   ELSIF (D=X"FB") THEN
       CNT1:=6;
   END IF;

   IF (Cnt=0) THEN
      Cnt:=Cnt1;
     Clk_OUT<='1';
   ELSE
     Cnt:=Cnt-1;
     Clk_OUT<='0';
   END IF;
END IF;
END PROCESS;
END ARCH_FRE_DIV;

不知道哪有问题,,我自己的网上下的程序都编译通过了,,应该不是姓名问题

要不麻烦看下

我领导要求是
00000000    不分
00000001     2分
00000010     4分
00000011     6分
00000100     8分
00000101     10
00000110     12
00000111     14
00001000     16
依次类推

看有好办法不??

eeleader

楼上兄弟，我把程序在QUARTUSII 9.0 中编译了一下，没问题程序如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY  FRE_DIV1  IS
PORT
   (CLK : IN STD_LOGIC;
    D     : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
    H     : OUT STD_LOGIC
   );
END ENTITY;
ARCHITECTURE ARCH_FRE_DIV1 OF FRE_DIV1 IS
SIGNAL CLK_OUT : STD_LOGIC;
BEGIN
PROCESS(CLK)
BEGIN
  IF (D=X"00") THEN
   H<=CLK;
  ELSE
   H<=CLK_OUT;
  END IF;
END PROCESS;
PROCESS(CLK)
VARIABLE CNT,CNT1 : INTEGER RANGE 0 TO 200;
BEGIN
IF CLK'EVENT AND CLK='1' THEN
   IF (Cnt=0) THEN
      Cnt:=(2*CONV_INTEGER(D)-1);
     Clk_OUT<='1';
   ELSE
     Cnt:=Cnt-1;
     Clk_OUT<='0';
   END IF;
END IF;
END PROCESS;
END ARCH_FRE_DIV1;
你把文件名改为FRE_DIV1，OK在ISE里面编译即可，完全满足你老师的要求

eeleader

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY  FRE_DIV1  IS
PORT
   (CLK : IN STD_LOGIC;
    D     : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
    H     : OUT STD_LOGIC
   );
END ENTITY;
ARCHITECTURE ARCH_FRE_DIV1 OF FRE_DIV1 IS
SIGNAL CLK_OUT : STD_LOGIC;
BEGIN
PROCESS(CLK)
BEGIN
  IF (D=X"00") THEN
   H<=CLK;
  ELSE
   H<=CLK_OUT;
  END IF;
END PROCESS;
PROCESS(CLK)
VARIABLE CNT,CNT1 : INTEGER RANGE 0 TO 2000;
BEGIN
IF CLK'EVENT AND CLK='1' THEN
   IF (Cnt=0) THEN
      Cnt:=(2*CONV_INTEGER(D)-1);
     Clk_OUT<='1';
   ELSE
     Cnt:=Cnt-1;
     Clk_OUT<='0';
   END IF;
END IF;
END PROCESS;
END ARCH_FRE_DIV1;
这个程序是最终de, VARIABLE CNT,CNT1 : INTEGER RANGE 0 TO 2000;只是这句话休改了一下，把200改为2000。否则计数器的范围小了

zhuzhouren

刚才编译可以了..真好人也..我想问下这个只能实现偶数分频的吧??

flanix

这样分频也太累了吧。

eeleader

完全按照你老师的要求，只能实现偶数分频

zhuzhouren

还有个问题就是编译过了,,仿真过不了,,,

ERROR:HDLCompiler:488 - "D:/pyytszy/pyyy/pppp.vhd" Line 68: Illegal identifier : _period
ERROR:HDLCompiler:488 - "D:/pyytszy/pyyy/pppp.vhd" Line 70: Illegal identifier : _process
ERROR:HDLCompiler:488 - "D:/pyytszy/pyyy/pppp.vhd" Line 73: Illegal identifier : _period
ERROR:HDLCompiler:488 - "D:/pyytszy/pyyy/pppp.vhd" Line 75: Illegal identifier : _period
ERROR:HDLCompiler:488 - "D:/pyytszy/pyyy/pppp.vhd" Line 85: Illegal identifier : _period
Analyzing VHDL file "D:/pyytszy/pyyy/netgen/fit/FRE_DIV1_timesim.vhd" into library work
Analyzing VHDL file "D:/pyytszy/pyyy/pppp.vhd" into library work
ERROR:HDLCompiler:806 - "D:/pyytszy/pyyy/pppp.vhd" Line 68: Syntax error near constant.
ERROR:HDLCompiler:488 - "D:/pyytszy/pyyy/pppp.vhd" Line 68: Illegal identifier : _period
VHDL file D:/pyytszy/pyyy/pppp.vhd ignored due to errors
ERROR:HDLCompiler:841 - "D:/pyytszy/pyyy/pppp.vhd" Line 68: Expecting type  void for .
ERROR:HDLCompiler:488 - "D:/pyytszy/pyyy/pppp.vhd" Line 70: Illegal identifier : _process
ERROR:HDLCompiler:806 - "D:/pyytszy/pyyy/pppp.vhd" Line 72: Syntax error near <.
ERROR:HDLCompiler:488 - "D:/pyytszy/pyyy/pppp.vhd" Line 73: Illegal identifier : _period
ERROR:HDLCompiler:488 - "D:/pyytszy/pyyy/pppp.vhd" Line 75: Illegal identifier : _period
ERROR:HDLCompiler:806 - "D:/pyytszy/pyyy/pppp.vhd" Line 85: Syntax error near <.
ERROR:HDLCompiler:488 - "D:/pyytszy/pyyy/pppp.vhd" Line 85: Illegal identifier : _period
ERROR:HDLCompiler:854 - "D:/pyytszy/pyyy/pppp.vhd" Line 36: Unit ignored due to previous errors.


ISE仿真出现上书问题,,我自己的编的那个程序不能实现2分频和原样输出,,仿真过了,,迫切希望高人解答

zhuzhouren

我自己编写的就是功能少了2分频和原样输出,,所以交差不了,,,

eeleader

欢迎5楼兄弟，写出更好的程序！

zhuzhouren

版主  程序编译过了防真不过去...哪个地方有问题?/

eeleader

仿真为啥过不去？原因。

eeleader

我刚才自己在QUARTUSII 9.0中仿真，没有任何问题！

eeleader

分频程序仿真

eeleader

zhuzhouren， 是你仿真配置不对，你对ISE怎样仿真没搞对而已

zhuzhouren

library ieee;
use ieee.std_logic_1164.all;
entity clk_div is
generic(n:integer:=2);--n的值是要分频的系数，n>=2
    port (clock : in std_logic:='0';
          clk_out : out std_logic);
end clk_div;
architecture sea of clk_div is
signal temp : std_logic:='0';

begin
process(clock,temp)
variable a,a1,a2 : integer range 0 to n;
variable temp1,temp2 : std_logic:='0';
begin
if (n rem 2)=1 then
if rising_edge(clock) then
    if a1=n-1 then a1:=0;temp1:='0';
    elsif a1<((n+1)/2-1) then temp1:='1';a1:=a1+1;
       elsif a1>=((n+1)/2-1) then temp1:='0';a1:=a1+1;
    end if;
end if;
if falling_edge(clock) then
    if a2=n-1 then a2:=0;temp2:='0';
    elsif a2<((n+1)/2-1) then temp2:='1';a2:=a1+1;
       elsif a2>=((n+1)/2-1) then temp2:='0';a2:=a2+1;
    end if;
end if;
temp<=temp1 or temp2;
elsif rising_edge(clock) then
    if a=(n/2-1) then a:=0;temp<=not temp;
    else a:=a+1;
    end if;
end if;
end process;
clk_out<=temp;
end sea;


这个是论坛上另外一个程序,,编译防真我都过了,,没出现过任何问题,,防真图形如附件,,我同样的操作,,但是 对这个程序编译可以,,防真就报如下,,操作了3遍

ERROR:HDLCompiler:488 - "D:/fffdff/uiuiu/popopop.vhd" Line 68: Illegal identifier : _period
ERROR:HDLCompiler:488 - "D:/fffdff/uiuiu/popopop.vhd" Line 70: Illegal identifier : _process
ERROR:HDLCompiler:488 - "D:/fffdff/uiuiu/popopop.vhd" Line 73: Illegal identifier : _period
ERROR:HDLCompiler:488 - "D:/fffdff/uiuiu/popopop.vhd" Line 75: Illegal identifier : _period
ERROR:HDLCompiler:488 - "D:/fffdff/uiuiu/popopop.vhd" Line 85: Illegal identifier : _period
Analyzing VHDL file "D:/fffdff/uiuiu/netgen/fit/FRE_DIV1_timesim.vhd" into library work
Analyzing VHDL file "D:/fffdff/uiuiu/popopop.vhd" into library work
VHDL file D:/fffdff/uiuiu/popopop.vhd ignored due to errors
ERROR:HDLCompiler:806 - "D:/fffdff/uiuiu/popopop.vhd" Line 68: Syntax error near constant.
ERROR:HDLCompiler:488 - "D:/fffdff/uiuiu/popopop.vhd" Line 68: Illegal identifier : _period
ERROR:HDLCompiler:841 - "D:/fffdff/uiuiu/popopop.vhd" Line 68: Expecting type  void for .
ERROR:HDLCompiler:488 - "D:/fffdff/uiuiu/popopop.vhd" Line 70: Illegal identifier : _process
ERROR:HDLCompiler:806 - "D:/fffdff/uiuiu/popopop.vhd" Line 72: Syntax error near <.
ERROR:HDLCompiler:488 - "D:/fffdff/uiuiu/popopop.vhd" Line 73: Illegal identifier : _period
ERROR:HDLCompiler:488 - "D:/fffdff/uiuiu/popopop.vhd" Line 75: Illegal identifier : _period
ERROR:HDLCompiler:806 - "D:/fffdff/uiuiu/popopop.vhd" Line 85: Syntax error near <.
ERROR:HDLCompiler:488 - "D:/fffdff/uiuiu/popopop.vhd" Line 85: Illegal identifier : _period
ERROR:HDLCompiler:854 - "D:/fffdff/uiuiu/popopop.vhd" Line 36: Unit ignored due to previous errors.

eeleader

我知道问题了，modsim 仿真不支持CON_INTEGER(D)这个函数！

eeleader

MODESIM 仿真需要把信号初始值

zhuzhouren

那 版主可以具体帮我下不?麻烦

eeleader

一定要MODESIM 仿真吗？

zhuzhouren

因为我用是XINLIN的芯片,,,网上下的很多程序编译防真都可以过的了,,所以这个程序我也想防真过去,,老卡住