vsim-SDF-3250错误处理

teleagle

vsim-SDF-3250错误处理 [复制链接]

libero soc 11.8

在电路综合后仿真正常的情况下,  时序仿真却报: vsim-SDF-3250 错误,  如下所示:


# ** Error: (vsim-3170) Could not find 'D:\Test_Designs\ModelSim_Wrong_Project_Settings\verilog_flow\designer\impl1\simulation\postlayout.testbench'.
# Error loading design
# Error: Error loading design

# ** Error: (vsim-SDF-3250) D:/Test_Designs/ModelSim_Wrong_Project_Settings/verilog_flow/designer/impl1/top_ba.sdf(0): Failed to find INSTANCE '/top_0'.
# ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s).
# Loading proasic3.Dffpr
# Loading proasic3.UDP_MUX2
# ** Error: (vsim-SDF-3250) D:/Test_Designs/ModelSim_Wrong_Project_Settings/verilog_flow/designer/impl1/top_ba.sdf(0): Failed to find INSTANCE '/top_0'.
# Error loading design

处理方法:
1.首先检查仿真设置是否正确:

右键 Simulate --> 选择 Organize Stimulus Files...   --> 检查激激励文件设置是否正确.    以及SDF文件是否 USER

2.进项目设置修改

Project   -->   Project Settings...  -->  左边选择 "Do file" 项 ---->  在右边"Top level instance name" 栏,  填入激励文件中,被测试模块的例化 名,  --- >  Save  

3.  再次启动 ModelSim 进行时序仿真, 祝成功!!