Altera参考设计-Stratix 高速率数据接口

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Altera参考设计-Stratix 高速率数据接口 [复制链接]

High-Speed Data Interface for Stratix Devices &Fujitsu MB86064 DACs

Introduction
Implementing the digital interface to drive a high-speed digital-to-analogue converter (DAC) is challenging. The conversion rates of high-speed DACs has increased significantly in recent years, so special design techniques are required to ensure data integrity.

This application note describes a reference design that implements a high-speed data interface between a Stratix™ device and a Fujitsu MB86064 DAC. The interface comprises two 14-bit parallel buses, each running at up to 800 million samples per second (MSPS). A key feature of the reference design combines the Stratix enhanced phase-locked loop (PLL) with the MB86064 loop-clock facility to maintain optimum clock-to-data timing.