out出不来
<p>我用modesim仿真</p><p>register.v:</p>
<pre>
<code>module register8(ena,clk,data,rst,out);
input ena,clk,rst;
input data;
output out;
wire data;
reg out;
always @(posedge clk)
if (!rst)
out = 0;
else if (ena)
out = data;
//閾忕晫鍔у▽鈩冩箒閸愭獔lse妞ょ櫢绱濋弰鍓у姧婵″倹鐏塭na娑撹桨缍嗛悽闈涢挬閿涘苯宓嗘担鎸庢闁界喎褰夐崠鏍电礉data閸欐ê瀵查敍灞肩稻out娴犲秳绻氶幐浣风瑝閸?
endmodule
</code></pre>
<p>register1.v</p>
<pre>
<code>// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors.Please refer to the
// applicable agreement for further details.
// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to
// suit user's needs .Comments are provided in each section to help the user
// fill out necessary details.
// *****************************************************************************
// Generated on "06/08/2024 07:43:11"
// Verilog Test Bench template for design : register8
//
// Simulation tool : ModelSim (Verilog)
//
`timescale 1 ns/ 100 ps
module register8_vlg_tst();
// constants
// general purpose registers
// test vector input registers
reg clk;
reg data;
reg ena;
reg rst;
// wires
wire out;
// assign statements (if any)
register8 i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.data(data),
.ena(ena),
.out(out),
.rst(rst)
);
initial
begin
// code that executes only once
// insert code here --> begin
clk=0;
#5 clk=~clk;
// --> end
end
initial
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
#10 rst=0;
#10 rst=1;
#10 ena=1;
#10 data=16'h55;
#10 data=16'haa;
#10 data=16'h46;
#10 $stop;
// --> end
end
endmodule
</code></pre>
<p>仿真效果图：<br />
</p>
<div style="text-align: center;"></div>
<div style="text-align: center;">请问高手，哪里出错了？谢谢！</div>
<p> </p>
设置中断，二分查找吧 <p>testbench中第54行前面加个always，你这时钟一直为1，结果肯定不对。</p>
00750 发表于 2024-6-8 10:21
testbench中第54行前面加个always，你这时钟一直为1，结果肯定不对。
<p>谢谢！</p>
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