Help！FPGA

mengfk11

Help！FPGA [复制链接]

Modelsim 中写了个测试文件，出现如下错误，那位大神能解决一下啊！

** Error: C:/altera/91/modelsim_ase/exise/work/test.vt(49): Undefined variable: KF_Filter.

** Error: C:/altera/91/modelsim_ase/exise/work/test.vt(49): near "U1": syntax error, unexpected "IDENTIFIER"

KF_Filter是顶层模块
测试源程序如下

`timescale 1 ns/ 100 ps

`define cycle 10

//`include"KF_Filter.v"

//`include"STEP1.v"

module KF_Filter_vlg_tst();

reg [31:0] at_0;

reg clk;

reg [31:0] ke_0;

reg reset;

reg [31:0] vt_0;

// wires

wire [31:0] at_1;

wire [31:0] vt_1;

always #`cycle clk=~clk;

initial begin

clk=1'b0;

at_0=32'h00000000;//at=0

vt_0=32'h00000000;//vt=2.944

ke_0=32'h00000000;

reset=1'b1;

end

initial begin

begin ///because of the coppute one value nee 3.7ms

//so the sample data need given time is 4ms

#(200000*`cycle)begin //4ms

reset=1'b1;

at_0=32'h00000000;//at=0

vt_0=32'h3C23D70A;//vt=2.944

ke_0=32'h3C23D70A;

end

#(200000*`cycle)begin

at_0=32'h3F4CCCCD;//at=0.8

vt_0=32'h3F4CCCCD;//vt=3.4

ke_0=32'h3C23D70A;

end

#(100*`cycle) $stop;

end

KF_Filter U1 (

// port map - connection between master ports and signals/registers

.at_0(at_0),

.at_1(at_1),

.clk(clk),

.ke_0(ke_0),

.reset(reset),

.vt_0(vt_0),

.vt_1(vt_1)

);

endmodule

chenzhufly

英文都看不懂吗？

没有这个KF_Filter

eeleader

KF_FILTER这个变量没有定义~！

KF_Filter： U1 (