// led.v
module led(a,b,o1,o2);
input a,b;
output o1,o2;
reg o1,o2,m;
[email=always@(a]always@(a[/email] or b)
begin
if(a==0)
begin
if(b==0)m=2;
else m=1;
end
else if(b==0)
begin
m=1;
end
else m=0;
if(m==1)begin
o1=0;
o2=1;
end
else if(m==2)
begin
o1=1;
o2=0;
end
else begin
o1=1;
o2=1;
end