源代码如下:
library ieee;
use ieee.std_logic_1164.all;
entity state is
port(
clk,reset:in std_logic;
input : in std_logic_vector(0 to 1);
sel : buffer std_logic_vector(0 to 2); --片选
show : out std_logic_vector(0 to 6); --八位七段
output:out std_logic_vector(0 to 1)
);
end state;
architecture behave of state is
type s_m is (s0,s1,s2,s3,s5,s6);
signal current_state,next_state:s_m;
begin
sel<="000";
process(reset,clk)
begin
if (clk'event and clk='1') then
current_state<=next_state;
if reset='1' then
current_state<=s0;
end if;
end if;
end process;
process(current_state,input)
begin
case current_state is
when s0=>output<="00";
show<="1111110"; --0
if input="00" then next_state<=s0;
elsif input="01" then next_state<=s1;
elsif input="10" then next_state<=s2;
elsif input="11" then next_state<=s5;
end if;
when s1=>output<="00";
show<="0110000"; --1
if input="00" then next_state<=s1;
elsif input="01" then next_state<=s2;
elsif input="10" then next_state<=s3;
elsif input="11" then next_state<=s6;
end if;
when s2=>output<="11";
show<="0110111"; --H
if input="00" then next_state<=s0;
elsif input="01" then next_state<=s1;
elsif input="10" then next_state<=s2;
elsif input="11" then next_state<=s5;
end if;
when s3=>output<="11";
show<="0110000"; --找1
if input="00" then next_state<=s0;
elsif input="01" then next_state<=s1;
elsif input="10" then next_state<=s2;
elsif input="11" then next_state<=s5;
end if;
when s5=>output<="11";
show<="0110000"; --找1
if input="00" then next_state<=s0;
elsif input="01" then next_state<=s1;
elsif input="10" then next_state<=s2;
elsif input="11" then next_state<=s5;
end if;
when s6=>output<="11";
show<="0110111"; --H
if input="00" then next_state<=s0;
elsif input="01" then next_state<=s1;
elsif input="10" then next_state<=s2;
elsif input="11" then next_state<=s5;
end if;