iCE65 mobileFPGAs? 应用在手机上的FPGA 产品

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iCE65 mobileFPGAs? 应用在手机上的FPGA 产品 [复制链接]

Handheld designers of battery-based consumer products have long awaited a programmable logic solution, with maximum design flexibility and fastest time-to-market, which also meets their price, power, space and logic capacity requirements. This solution, previously unattainable by other FPGA suppliers, is now provided by SiliconBlue’s new iCE65 mobileFPGA?. The iCE65 ultra-low power, ASIC-like, single-chip, SRAM mobileFPGA family has set new standards for programmable logic solutions by combining ultra low power, low cost and small form factor into a single-chip solution. The portfolio offers a full spectrum of device options optimized for logic density, power, I/O count and package size. Operating power as low as 8µW make the iCE65 mobileFPGAs ideal for applications where optimizing or extending battery life is key. Logic capacity ranges from ~60K to ~384K FPGA system gates, I/O counts from 48 to 222 and package sizes as small as 3mm by 4mm provide the best solution for each logic design need. Industry’s Lowest Standby Mode at Only 15µA[/td][td][/td][/tr][tr][td][/td][td][/td][td][/td][/tr][tr][td][/td][td]A large portion of handheld applications have a 32 kHz standby mode in order to meet green power requirements. Most FPGA solutions today require some form of power-down mode, with an associated recovery time that ranges from microseconds to milliseconds. iCE65 ultra-low power mobileFPGAs, running at only 15µA, allow battery-based applications to run in standby mode and monitor external stimuli such as keyboard clicks to wake up. There is no recovery time and the application responds instantaneously SiliconBlue ultra-low power FPGAs operate from a 1.0V core and consume 50% less static power and >50% less dynamic power than 1.8 V "low-power" competitive PLD alternatives. Benchmarks run against competing FPGA devices utilizing 192 16-bit counters (3.5K worth of LUTs) indicate that the iCE65 FPGAs offer the lowest-power versus frequency, even when compared to Flash and Anti-fuse based devices from the same class. Below is a graph that represents the power versus frequency curve in all major low power FPGAs and PLDs. [

SiliconBlue iCE65 Ultra-Low Power Leader

ASIC-Like FPGAs – Best of Both Worlds When comparing key attributes of other logic solutions, you find that Traditional FPGAs falter in the consumer hand held market for multiple reasons. Flash FPGAs as well as CPLDs have different problems which make them a non-optimal solution. ASICs do solve many of those market-critical requirements (cost/logic, single chip and low power) and hence have been successful with consumer, handheld designers. The iCE65 mobileFPGA, being low cost, ultra-low power and single chip, brings the key benefits of ASICs together with the high-value benefits of programmability, i.e.,

SiliconBlue iCE65 benefits versus traditional FPGAs/CPLDs & ASICs

WLCSP: The Best Package is No Package When minimizing board space in mobile applications becomes critical, designers need a programmable logic solution that not only has excellent price/performance but also comes in the smallest package possible. The new die-sized iCE65 mobileFPGA Wafer Level Chip Scale Package solutions from SiliconBlue provide the smallest, lowest cost FPGA solution by eliminating expensive substrates and gold wire bonding. The iCE65L04 and iCE65L08 options offer mobile handheld designers new, small form factor solutions at 3.2mm x 3.9mm with 0.4mm ball pitch and at 4.4mm x 4.8mm with 0.5mm ball pitch, respectively. The combination of high-density logic and ultra-small WLCSPs provides designers the ability to integrate up to 17x more logic functionality into the same board space versus competing Flash FPGA/CPLDs. Compared to standard surface-mount packaging, WLCSPs also provide reduced chip-to-PCB inductance and improved thermal dissipation. In addition, all package dimensions meet industry standard JEDEC/EIAJ pitches, making them directly compatible with today’s SMT assembly and test.

SiliconBlue WLCSP - 4.4mm x 4.8mm with 0.5mm ball pitch

New Turbo (-T) Speed Option Optimized for high speed using TSMC’s 65nm low power CMOS process, the 65% faster “turbo” speed grade addresses a growing requirement in consumer mobile applications where higher speed logic solutions in battery-based handheld applications are necessary. Combined with the industry’s only wafer level chip scale package SRAM FPGA, the iCE65 turbo product now offers a complete, unbeatable solution of high speed devices with the lowest power levels, housed within the smallest PCB foot print.

Speed & Power Comparison

Low Power 65nm CMOS Process SRAM FPGAs have dominated programmable logic due to the low cost afforded by leading edge, high performance process nodes. Now, SiliconBlue is applying this leading edge strategy to build low power FPGAs by utilizing TSMC's 65nm LP, low power process node. Previous leading process nodes were high performance, high power and not suitable for portable, battery powered application design requirements. Beginning at 65nm, however, the trend has switched to low power, LP, as the first available on a new process node. [/td][td][/td][/tr][tr][td][/td][td][/td][td][/td][/tr][tr][td][/td][td]Advantages of the leading process node are, of course, smaller transistors, providing higher logic capacity and lower capacitance at lower core voltage, resulting in lower active power, proportional to CV2. Higher logic capacity translates into lower cost per unit logic when compared to older specialty process nodes from other FPGA suppliers

SiliconBlue iCE65 65nm CMOS die

Die Stacking using mobileFPGAs Also available in die form, the ultra-low power “ASIC-like” mobileFPGAs provide system designers and ASSP vendors with a new, high density “3-D stacking” option (SiPs). As the figures shows below, using industry standard techniques, designers can now stack their current application processor chips with the KGD iCE65 mobileFPGAs and deliver new products, with new features, quickly and easily without waiting 12-18 months for their next generation ASSP. Example of iCE65 FPGA stacked on Application Processor As the graphic below indicates, this innovative, best-of-both-breeds stacking solution also significantly reduces design costs, risk and improves time-to-market