Virtex-6 FPGA User Guide

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Virtex-6 FPGA User Guide [复制链接]

Configurable Logic Block User Guide

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Virtex®-6 devices.

[ 本帖最后由 凯哥 于 2009-7-28 14:31 编辑 ]

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This guide describes the System Monitor functionality.

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This guide describes the DSP48E1 slice in Virtex®-6 FPGAs and includes configuration examples.

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This guide describes the Virtex®-6 device block RAM and FIFO capabilities.

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This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.

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This guide describes the SelectIO™ resources available in all the Virtex®-6 devices.

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This guide describes the clocking resources available in all the Virtex®-6 devices, including the MMCM and Clock Buffers.

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This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

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This guide describes the GTX transceivers available in all the Virtex®-6 FPGAs except the XC6VLX760.

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This guide describes the dedicated tri-mode Ethernet media access controller (TEMAC) available in all the Virtex®-6 FPGAs except the XC6VLX760.