推荐下载，非常不错的电子书hardware_design_verification.chm

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Copyright
     Prentice Hall Modern Semiconductor Design Series
     Preface
        To the Audience
        To the Instructor
        Organization of the Book
        Errata
     Acknowledgments
     About the Author
         Chapter 1.  An Invitation to Design Verification
        Section 1.1.  What Is Design Verification?
        Section 1.2.  The Basic Verification Principle
        Section 1.3.  Verification Methodology
        Section 1.4.  Simulation-Based Verification versus Formal Verification
        Section 1.5.  Limitations of Formal Verification
        Section 1.6.  A Quick Overview of Verilog Scheduling and Execution Semantics
        Section 1.7.  Summary
         Chapter 2.  Coding for Verification
        Section 2.1.  Functional Correctness
        Section 2.2.  Timing Correctness
        Section 2.3.  Simulation Performance
        Section 2.4.  Portability and Maintainability
        Section 2.5.  "Synthesizability," "Debugability," and General Tool Compatibility
        Section 2.6.  Cycle-Based Simulation
        Section 2.7.  Hardware Simulation/Emulation
        Section 2.8.  Two-State and Four-State Simulation
        Section 2.9.  Design and Use of a Linter
        Section 2.10.  Summary
        Section 2.11.  Problems
         Chapter 3.  Simulator Architectures and Operations
        Section 3.1.  The Compilers
        Section 3.2.  The Simulators
        Section 3.3.  Simulator Taxonomy and Comparison
        Section 3.4.  Simulator Operations and Applications
        Section 3.5.  Incremental Compilation
        Section 3.6.  Simulator Console
        Section 3.7.  Summary
        Section 3.8.  Problems
         Chapter 4.  Test Bench Organization and Design
        Section 4.1.  Anatomy of a Test Bench and a Test Environment
        Section 4.2.  Initialization Mechanism
        Section 4.3.  Clock Generation and Synchronization
        Section 4.4.  Stimulus Generation
        Section 4.5.  Response Assessment
        Section 4.6.  Verification Utility
        Section 4.7.  Test Bench-to-Design Interface
        Section 4.8.  Common Practical Techniques and Methodologies
        Section 4.9.  Summary
        Section 4.10.  Problems
         Chapter 5.  Test Scenarios, Assertions, and Coverage
        Section 5.1.  Hierarchical Verification
        Section 5.2.  Test Plan
        Section 5.3.  Pseudorandom Test Generator
        Section 5.4.  Assertions
        Section 5.5.  SystemVerilog Assertions
        Section 5.6.  Verification Coverage
        Section 5.7.  Summary
        Section 5.8.  Problems
         Chapter 6.  Debugging Process and Verification Cycle
        Section 6.1.  Failure Capture, Scope Reduction, and Bug Tracking
        Section 6.2.  Simulation Data Dumping
        Section 6.3.  Isolation of Underlying Causes
        Section 6.4.  Design Update and Maintenance: Revision Control
        Section 6.5.  Regression, Release Mechanism, and Tape-out Criteria
        Section 6.6.  Summary
        Section 6.7.  Problems
         Chapter 7.  Formal Verification Preliminaries
        Section 7.1.  Sets and Operations
        Section 7.2.  Relation, Partition, Partially Ordered Set, and Lattice
        Section 7.3.  Boolean Functions and Representations
        Section 7.4.  Boolean Functional Operators
        Section 7.5.  Finite-State Automata and Languages
        Section 7.6.  Summary
        Section 7.7.  Problems
         Chapter 8.  Decision Diagrams, Equivalence Checking, and Symbolic Simulation
        Section 8.1.  Binary Decision Diagrams
        Section 8.2.  Decision Diagram Variants
        Section 8.3.  Decision Diagram-Based Equivalence Checking
        Section 8.4.  Boolean Satisfiability
        Section 8.5.  Symbolic Simulation
        Section 8.6.  Summary
        Section 8.7.  Problems
         Chapter 9.  Model Checking and Symbolic Computation
        Section 9.1.  Properties, Specifications, and Logic
        Section 9.2.  Property Checking
        Section 9.3.  Symbolic Computation and Model Checking
        Section 9.4.  Symbolic CTL Model Checking
        Section 9.5.  Computational Improvements
        Section 9.6.  Using Model-Checking Tools
        Section 9.7.  Summary
        Section 9.8.  Problems
     Bibliography

nikel

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