职位名称:资深ASIC验证工程师
Position title: Senior ASIC Verification Engineer
1. Responsibilities:
1) Working within an ASIC design team to develop reusable block-level and ASIC testbenches using high-level verification language (System Verilog).
2) Develop new ASIC verification environments to support ASIC development.
3) Review RTL architectural and implementation specifications.
4) Create stimulus drivers, monitors, dataflow models, and test plans to verify function and performance of advanced SOC ASICs.
5) Define and implement code/functional coverage plans.
6) Develop testing and regression methodologies for new verification flow.
7) Incorporate reusability into all aspects of the verification environment.
8) Develop/maintain/enhance environment tools/scripts/makefiles.
2. Qualification:
1) Minimum of 3 years ASIC verification experience in a product development environment with proven ASIC design verification skills
2) Experience in using event-driven simulators like VCS
3) Fluent in Verilog for design verification
4) Experience in writing testbench using System Verilog
5) Knowledge of peripheral IP intergration (PCI, USB2.0, PCI)
6) Knowledge of AMBA/AHB/DMA
7) Experience with one or more scripting languages: Perl, TCL, Shell
8) Superior debugging skills for large ASIC designs
9) Strong written and verbal communication skills
3. Required Degree:
MS Preferred Major: Electrical Engineering or related discipline
Position title: Communication System Engineer
1. Responsibilities:
(1) Develop core algorithms in C/C++ for UWB (OFDM) receiver;
(2) Perform simulation tasks and optimization in performance, complexity and memory requirement;
(3) Perform fixed point C optimization;
(4) Come up with PHY ASIC architecture with PHY ASIC group.
2. Qualification:
(1) Solid experience in OFDM system algorithm development;
(2) Proficient in C/C++/Matlab programming;
(3) Thorough understanding of communication system;
(4) Experience in FPGA/ASIC implementation of PHY.
3. Priority:
Wireless communication experience;
Fixed point optimization experience;
FPGA mapping experience;.
PHY ASIC micro architecture experience;
Ph.D.