P5SEL |= 0x0C; // Port select XT2
UCSCTL6 &= ~XT2OFF; // Enable XT2
UCSCTL3 |= SELREF_2; // FLLref = REFO
// Since LFXT1 is not used,
// sourcing FLL with LFXT1 can cause
// XT1OFFG flag to set
UCSCTL4 |= SELA_2; // ACLK=REFO,SMCLK=DCO,MCLK=DCO
// Loop until XT1,XT2 & DCO stabilizes
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
UCSCTL6 &= ~XT2DRIVE0; // Decrease XT2 Drive according to
// expected frequency
UCSCTL4 |= SELS_5 + SELM_5; // SMCLK=MCLK=XT2
P1DIR |= BIT0; // P1.0 output
for(i=0;i<10240;i++)
{
buffer0[i] = i % 256;
}
while(1)
{
for(i=0;i<10240;i++)
P1OUT = buffer0[i];
}
}
int __low_level_init(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop WDT
/* Insert your low-level initializations here */
/*
* Return value:
*
* 1 - Perform data segment initialization.
* 0 - Skip data segment initialization.
*/