TI公司的MSP430F5529的A/D转换模块在P1.6输入端,名称为ADC12,是用12位数字寄存器保存转换结果的AD转换器。
***转换有两个参考电压,最高电压VR+,最低电压VR-作为转换的上下限,高于等于VR+输出0FFF,小于等于VR-输出0000,待转换模拟电压Vin转换后的数字量计算为Data=4095 x (Vin-VR-)/(VR+ -VR-),程序结构如下
#include "msp430F5529.h"
int tt=0,temp,kk;
void delay(int ns)
{
while(ns--);
}
//******A/D转换函数设置*****//
void adc1()
{
P1SEL |=BIT6; //转换模拟信号从P1.6输入,内部集成了转换模块
ADC12CTL0 =ADC12ON + ADC12SHT0_8 + ADC12MSC;
ADC12CTL1 =ADC12SHP + ADC12CONSEQ_2;
ADC12MCTL0=ADC12SREF_0+ADC12INCH_6;
ADC12CTL0 |=ADC12ENC;
//////一次转换结束后产生转换中断调用ADC中断函数////
}
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
UCSCTL3 |=SELREF__REFOCLK;
__bis_SR_register(SCG0); //disable the FLL control loop
UCSCTL0=0X0000;// //Set lowest possible DCOx,MODxSCG0
UCSCTL1=DCORSEL_7; //Select DCO range 24MHz opreation
//DCORSEL_x,其中x可选3、4、5、6、7
UCSCTL3=FLLD_0+731; //Set DCO Multiplier for 24MHz
//(N+1)*FLLRef=Fdco
//(731+1)*32768=24MHz
//Set FLL DIV =fDCOCLK/2
/*__bis_SR_register(SCG0); //Enable the FLL control loopSCG0
UCSCTL4 |=SELA__DCOCLK+SELS__XT1CLK+SELM__DCOCLK;//MCLK Source select
UCSCTL5 |=DIVPA_2; //ACLK output divide
UCSCTL6 |=XT1DRIVE_3+XCAP_0; //XT1 cap */