ADC12模数转换是在SHI的上升沿初始化的。SHI信号有四个来源: The ADC12SC bit;The Timer_A Output Unit 1; The Timer_B Output Unit 0; The Timer_B Output Unit 1。故单次采样时只需要每次设置ADC12CTL0 |= ADC12SC就采样一次;重复采样时,如Rep-sing,设置ADC12CTL1 = SHS_1 +CONSEQ_2就选择了Rep-sing模式,每次采样通过定时器A触发。
3 相关寄存器
1、ADC12CTL0
SHT1x Bits
Sample-and-hold time. These bits define the number of ADC12CLK cycles in
the sampling period for registers ADC12MEM8 to ADC12MEM15.
SHT0x Bits
Sample-and-hold time. These bits define the number of ADC12CLK cycles in
the sampling period for registers ADC12MEM0 to ADC12MEM7.
ADC12ON
0 ADC12 off
1 ADC12 on
ENC
ENC Bit 1 Enable conversion
0 ADC12 disabled
1 ADC12 enabled
ADC12SC Bit 0 Start conversion. Software-controlled sample-and-conversion start.
ADC12SC and ENC may be set together with one instruction. ADC12SC is
reset automatically.
0 No sample-and-conversion-start
1 Start sample-and-conversion
MSC Bit 7 Multiple sample and conversion. Valid only for sequence or repeated modes.
0 The sampling timer requires a rising edge of the SHI signal to trigger
each sample-and-conversion.
1 The first rising edge of the SHI signal triggers the sampling timer, but
further sample-and-conversions are performed automatically as soon
as the prior conversion is completed.
2、ADC12CTL1
SHP
SHP Bit 9 Sample-and-hold pulse-mode select. This bit selects the source of the
sampling signal (SAMPCON) to be either the output of the sampling timer or
the sample-input signal directly.
0 SAMPCON signal is sourced from the sample-input signal.
1 SAMPCON signal is sourced from the sampling timer.
SHSx Bits
11-10
Sample-and-hold source select
00 ADC12SC bit
01 Timer_A.OUT1
10 Timer_B.OUT0
11 Timer_B.OUT1
CONSEQx Bits
2-1
Conversion sequence mode select
00 Single-channel, single-conversion
01 Sequence-of-channels
10 Repeat-single-channel
11 Repeat-sequence-of-channels
3、ADC12IE
ADC12IEx Bits
15-0
Interrupt enable. These bits enable or disable the interrupt request for the ADC12IFGx bits.
0 Interrupt disabled
1 Interrupt enabled
4、ADC12IFG
ADC12IFGx Bits
15-0
ADC12MEMx Interrupt flag. These bits are set when corresponding
ADC12MEMx is loaded with a conversion result. The ADC12IFGx bits are
reset if the corresponding ADC12MEMx is accessed, or may be reset with
software.
0 No interrupt pending
1 Interrupt pending
5、ADC12MCTLX
SREFx Bits
6-4
Select reference
000 VR+ = AVCC and VR− = AVSS
001 VR+ = VREF+ and VR− = AVSS
010 VR+ = VeREF+ and VR− = AVSS
011 VR+ = VeREF+ and VR− = AVSS
100 VR+ = AVCC and VR− = VREF−/ VeREF−
101 VR+ = VREF+ and VR− = VREF−/ VeREF−
110 VR+ = VeREF+ and VR− = VREF−/ VeREF−
111 VR+ = VeREF+ and VR− = VREF−/ VeREF−
INCHx Bits
3-0
Input channel select
0000 A0
0001 A1
0010 A2
0011 A3
0100 A4
0101 A5
0110 A6
0111 A7
1000 VeREF+
1001 VREF−/VeREF−
1010 Temperature sensor
1011 (AVCC – AVSS) / 2
1100 (AVCC – AVSS) / 2
1101 (AVCC – AVSS) / 2
1110 (AVCC – AVSS) / 2
1111 (AVCC – AVSS) / 2
EOS Bit 7 End of sequence. Indicates the last conversion in a sequence.