// Read status of H1 and set the expected polarity
if (H1_PORT & H1_PIN)
{
TIM2->CCER1 |= BIT1;
bHStatus |= BIT2;
}
else
{
TIM2->CCER1 &= (u8)(~(BIT1));
}
// Read status of H2 and set the expected polarity
if (H2_PORT & H2_PIN)
{
TIM2->CCER1 |= BIT5;
bHStatus |= BIT1;
}
else
{
TIM2->CCER1 &= (u8)(~(BIT5));
}
// Read status of H3 and set the expected polarity
if (H3_PORT & H3_PIN)
{
TIM2->CCER2 |= BIT1;
bHStatus |= BIT0;
}
else
{
TIM2->CCER2 &= (u8)(~(BIT1));
}
bHallStartStep = bHallSteps[Run_dir][bHStatus];
if (bHallStartStep == 7)//不该出现的HALL状态
{
FaultF=1;
return;
}
// Read status of H1 and set the expected polarity
if (H1_PORT & H1_PIN)
{
TIM2->CCER1 |= BIT1;
bHStatus |= BIT2;
}
else
{
TIM2->CCER1 &= (u8)(~(BIT1));
}
// Read status of H2 and set the expected polarity
if (H2_PORT & H2_PIN)
{
TIM2->CCER1 |= BIT5;
bHStatus |= BIT1;
}
else
{
TIM2->CCER1 &= (u8)(~(BIT5));
}
// Read status of H3 and set the expected polarity
if (H3_PORT & H3_PIN)
{
TIM2->CCER2 |= BIT1;
bHStatus |= BIT0;
}
else
{
TIM2->CCER2 &= (u8)(~(BIT1));
}
if (TIM2->SR1 & BIT2)
{
TIM2->SR1=(u8)(~TIM2_IT_CC2);
}
if (TIM2->SR1 & BIT1)
{
TIM2->SR1=(u8)(~TIM2_IT_CC1);
}
if (TIM2->SR1 & BIT3)
{
TIM2->SR1=(u8)(~TIM2_IT_CC3);
}
// Read status of H1 and set the expected polarity
if (H1_PORT & H1_PIN)
{
TIM2->CCER1 |= BIT1;
bHStatus |= BIT2;
}
else
{
TIM2->CCER1 &= (u8)(~(BIT1));
}
// Read status of H2 and set the expected polarity
if (H2_PORT & H2_PIN)
{
TIM2->CCER1 |= BIT5;
bHStatus |= BIT1;
}
else
{
TIM2->CCER1 &= (u8)(~(BIT5));
}
// Read status of H3 and set the expected polarity
if (H3_PORT & H3_PIN)
{
TIM2->CCER2 |= BIT1;
bHStatus |= BIT0;
}
else
{
TIM2->CCER2 &= (u8)(~(BIT1));
}
bHallStartStep = bHallSteps[Run_dir][bHStatus];
if (bHallStartStep == 7)//不该出现的HALL状态
{
FaultF=1;
return;
}
// Read status of H1 and set the expected polarity
if (H1_PORT & H1_PIN)
{
TIM2->CCER1 |= BIT1;
bHStatus |= BIT2;
}
else
{
TIM2->CCER1 &= (u8)(~(BIT1));
}
// Read status of H2 and set the expected polarity
if (H2_PORT & H2_PIN)
{
TIM2->CCER1 |= BIT5;
bHStatus |= BIT1;
}
else
{
TIM2->CCER1 &= (u8)(~(BIT5));
}
// Read status of H3 and set the expected polarity
if (H3_PORT & H3_PIN)
{
TIM2->CCER2 |= BIT1;
bHStatus |= BIT0;
}
else
{
TIM2->CCER2 &= (u8)(~(BIT1));
}
if (TIM2->SR1 & BIT2)
{
TIM2->SR1=(u8)(~TIM2_IT_CC2);
}
if (TIM2->SR1 & BIT1)
{
TIM2->SR1=(u8)(~TIM2_IT_CC1);
}
if (TIM2->SR1 & BIT3)
{
TIM2->SR1=(u8)(~TIM2_IT_CC3);
}