signal TX:std_logic;
signal a:std_logic:='0';
signal b:std_logic:='0';
signal rx_shift_reg:std_logic_vector(7 downto 0):=(others=>'0');
signal rx_shift_reg_2:std_logic_vector(7 downto 0):=(others=>'0');
signal shift_cnt:std_logic_vector(3 downto 0):=(others=>'0');
signal shift_cnt_2:std_logic_vector(3 downto 0):=(others=>'0');
signal cnt:std_logic_vector(3 downto 0):=(others=>'0');
signal cnt_2:std_logic_vector(3 downto 0):=(others=>'0');
if rising_edge(spi_sck) then
if(a='1')then
rx_shift_reg<=rx_shift_reg(6 downto 0)& spi_din;
shift_cnt<=shift_cnt+1;
if(shift_cnt=x"07")then
b<='1';
a<=not a;
end if;
else
rx_shift_reg_2<=rx_shift_reg_2(6 downto 0)& spi_din;
shift_cnt_2<=shift_cnt_2+1;
if(shift_cnt_2=x"07")then
b<='0';
a<=not a;
end if;
end if;
end if;
if(b='1')then
if falling_edge(spi_sck) then
cnt<=cnt+1;
if(cnt=x"00")then
TX<=rx_shift_reg(7);
else
rx_shift_reg<=rx_shift_reg(6 downto 0)&'0';
TX<=rx_shift_reg(6);
if(cnt=x"07")then
cnt<=x"00";
end if;
end if;
end if;
else
if falling_edge(spi_sck) then
cnt_2<=cnt_2+1;
if(cnt_2=x"00")then
TX<=rx_shift_reg_2(7);
else
rx_shift_reg_2<=rx_shift_reg_2(6 downto 0)&'0';
TX<=rx_shift_reg_2(6);
if(cnt_2=x"07")then
cnt_2<=x"00";
end if;
end if;
end if;
end if;