Preface xvii
Why This Book Is Important
What This Book Is About
What Prior Knowledge You Should Have
Reading Paths
VHDL versus Verilog
For More Information
Acknowledgements xvii xviii xix xx xx xxii xxii CHAPTER 1 1 1 2 4 5 6 6 v
What is a Testbench?
The Importance of Verification
Reconvergence Model
The Human Factor Automation Poka-Yoka
Writing Testbenches: Functional Verification of HDL Models What is Verification?
Table of Content Redundancy 6 7 7 8 9 10 11 11 12 13 13 13 14 16 16 16 17 17 19 21 22 23 25 26 28 28 29 29 31 34 36 37 38 40 42 44 45
vi Writing Testbenches: Functional Verification of HDL Models
What Is Being Verified? Formal Verification Equivalence Checking Model Checking Functional Verification Testbench Generation
Functional Verification Approaches Black-Box Verification White-Box Verification Grey-Box Verification
Testing Versus Verification Scan-Based Testing Design for Verification
Verification and Design Reuse Reuse Is About Trust Verification for Reuse
The Cost of Verification
Summary CHAPTER 2 Verification Tools
Linting Tools The Limitations of Linting Tools Linting Verilog Source Code Linting VHDL Source Code Code Reviews
Simulators Stimulus and Response Event-Driven Simulation Cycle-Based Simulation Co-Simulators
Third-Party Models Hardware Modelers
Waveform Viewers
Code Coverage Statement Coverage Path Coverage Expression Coverage 45 46 47 48 50 51 52 52 53 54 55 55 57 57 58 59 60 61 62 62 63 64 65 66 67 68 68 69 70 71 72 73 73 74 75 75 76 77
Writing Testbenches: Functional Verification of HDL Models vii What Does 100 Percent Coverage Mean?
Verification Languages
Revision Control The Software Engineering Experience Configuration Management Working with Releases
Issue Tracking What Is an Issue? The Grapevine System The Post-It System The Procedural System Computerized System
Metrics Code-Related Metrics Quality-Related Metrics Interpreting Metrics
Summary CHAPTER 3 The Verification Plan
The Role of the Verification Plan Specifying the Verification Defining First-Time Success
Levels of Verification Unit-Level Verification Reusable Components Verification ASIC and FPGA Verification System-Level Verification Board-Level Verification
Verification Strategies Verifying the Response Random Verification
From Specification to Features Component-Level Features System-Level Features Error Types to Look For
From Features to Testcases Prioritize Group into Testcases Design for Verification
Table of Content 79 80 81
From Testcases to Testbenches Verifying Testbenches
Summary Behavioral Hardware Description Languages 83 83 85 87 87 88 91 92 93
94
97100101105112115121124125125126127128129132134137140141144146147147148viii Writing Testbenches: Functional Verification of HDL ModelsBehavioral versus RTL ThinkingContrasting the ApproachesYou Gotta Have Style!A Question of DisciplineOptimize the Right ThingGood Comments Improve MaintainabilityStructure of Behavioral CodeEncapsulation Hides Implementation DetailsEncapsulating Useful SubprogramsEncapsulating Bus-Functional ModelsData AbstractionReal ValuesRecordsMulti-Dimensional ArraysListsFilesInterfacing High-Level Data TypesThe HDL Parallel EngineConnectivity, Time, and Concurrency..Connectivity, Time, and Concurrency in HDLsThe Problems with ConcurrencyEmulating Parallelism on a Sequential ProcessorThe Simulation CycleParallel vs. SequentialFork/Join StatementThe Difference Between Driving and AssigningVerilog Portability IssuesRead/Write Race ConditionsWrite/Write Race ConditionsInitialization RacesGuidelines for Avoiding Race ConditionsEvents from Overwritten Scheduled ValuesDisabled Scheduled ValuesCHAPTER 4150151153155155156159160164165167169172172172174174176176177179183183184187189192193194195199202203205211211215216ixOutput Arguments on Disabled TasksNon-Reentrant TasksSummaryCHAPTER 5 Stimulus and ResponseSimple StimulusGenerating a Simple WaveformGenerating a Complex WaveformGenerating Synchronized WaveformsAligning Waveforms in Delta-TimeGenerating Synchronous Data WaveformsEncapsulating Waveform GenerationAbstracting Waveform GenerationVerifying the OutputVisual Inspection of ResponseProducing Simulation ResultsMinimizing SamplingVisual Inspection of WaveformsSelf-Checking TestbenchesInput and Output VectorsGolden VectorsRun-Time Result VerificationComplex StimulusFeedback Between Stimulus and DesignRecovering from DeadlocksAsynchronous InterfacesCPU OperationsConfigurable OperationsComplex ResponseWhat is a Complex Response?Handling Unknown or Variable LatencyAbstracting Output OperationsGeneric Output MonitorsMonitoring Multiple Possible OperationsMonitoring Bi-Directional InterfacesPredicting the OutputData FormattersPacket ProcessorsComplex TransformationsWriting Testbenches: Functional Verification of HDL ModelsTable of ContentSummary 219CHAPTER 6 Architecting Testbenches 221Reusable Verification Components 221225226227228231237238240243246247249250250253255255258258259260261262263265266268269269270271273x Writing Testbenches: Functional Verification of HDL ModelsProcedural InterfaceDevelopment ProcessVerilog ImplementationPackaging Bus-Functional ModelsUtility PackagesVHDL ImplementationPackaging Bus-Functional ProceduresCreating a Test HarnessAbstracting the Client/Server ProtocolManaging Control SignalsMultiple Server InstancesUtility PackagesAutonomous Generation and MonitoringAutonomous StimulusRandom StimulusInjecting ErrorsAutonomous MonitoringAutonomous Error DetectionInput and Output PathsProgrammable TestbenchesConfiguration FilesConcurrent SimulationsCompile-Time ConfigurationVerifying Configurable DesignsConfigurable TestbenchesTop Level Generics and ParametersSummaryCHAPTER 7 Simulation ManagementBehavioral ModelsBehavioral versus Synthesizable ModelsExample of Behavioral ModelingCharacteristics of a Behavioral ModelWriting Testbenches: Functional Verification of HDL Models xi276281285286286289289292294295301305309312313314316317318320320321321323326329329330332334334336336337337337340APPENDIX A Coding GuidelinesModeling ResetWriting Good Behavioral ModelsBehavioral Models Are FasterThe Cost of Behavioral ModelsThe Benefits of Behavioral ModelsDemonstrating EquivalencePass or Fail?Managing SimulationsConfiguration ManagementVerilog Configuration ManagementVHDL Configuration ManagementSDF Back-AnnotationOutput File ManagementRegressionRunning RegressionsRegression ManagementSummaryDirectory StructureVHDL SpecificVerilog SpecificGeneral Coding GuidelinesCommentsLayoutSyntaxDebuggingNaming GuidelinesCapitalizationIdentifiersConstantsHDL SpecificFilenamesHDL Coding GuidelinesStructureLayoutVHDL SpecificVerilog SpecificTable of ContentAfterwordsIndex347349
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