5509A程序运行时断开与仿真器连接

陌上花开zl

5509A程序运行时断开与仿真器连接 [复制链接]

CCS运行程序时将数组加进watch window老是断开与仿真器连接出现这样的错误，Trouble Reading Memory Block at 0x436 on Page 0 of Length 0x2c0: Error 0x80000002/-1143 Fatal Error during: Memory,  The memory at 0x000004A4 continually indicated it was 'not ready' All memory operations currently in progress were aborted in order to regain control of the processor. This is considered a catastrophic event, but the debugger should  still be able to access memory and CPU registers. System state has been altered.  It is strongly advised that the processor should be reset before resuming execution,   Sequence ID: 65 Error Code: -1143 Error Class: 0x80000002
有大神知道是什么原因吗？一星期了，一点头绪都没有。

dontium

楼主，把你的工作拿出来，让我参考一下，也好帮你找问题

陌上花开zl

谢谢您的回复，这两天忙着考试，所以没及时回复，程序挺多的，所以大神能加我qq吗763105321，谢谢谢谢了

陌上花开zl

dontium 发表于 2016-1-2 22:15
楼主，把你的工作拿出来，让我参考一下，也好帮你找问题

void main()
{
    int i;
    PLL_Init(100);
    wait(29);
    SDRAM_init();     
    AIC23_Init();
    INTR_init( );   
    TIMER_init( );
while(1)
    {
      if(TIME_flag==1)
      {
        TIME_flag=0;
        
        if(ID_time!=0)
        {        
           IDENTIFICATION();
           ID_time--;            
        }
        
        if(ID_time==0)
        {        
          if(ANC_flag==0)
          {
            ANC_flag=1;
            for(i=0;i             {
              Pu=0.0;
              uu=0.0;
              xxf=0.0;
              yy=0.0;              
              ee=0.0;
            }
          }
          FEEDFORWARD_ANC();
        }

      }   
    }
}
这部分是主程序
下面是AIC23.c
#define AIC23_LT_LINE_CTL         0x00  // 0
#define AIC23_RT_LINE_CTL         0x02  // 1
#define AIC23_LT_HP_CTL           0x04  // 2
#define AIC23_RT_HP_CTL           0x06  // 3
#define AIC23_ANALOG_AUDIO_CTL    0x08  // 4
#define AIC23_DIGITAL_AUDIO_CTL   0x0A  // 5
#define AIC23_POWER_DOWN_CTL      0x0C  // 6
#define AIC23_DIGITAL_IF_FORMAT   0x0E  // 7
#define AIC23_SAMPLE_RATE_CTL     0x10  // 8
#define AIC23_DIG_IF_ACTIVATE     0x12  // 9
#define AIC23_RESET_REG           0x1E  // F - Writing 0 to this reg triggers reset

// AIC23 Control Register settings
#define lt_ch_vol_ctrl       0x0017   /* 0  */
#define rt_ch_vol_ctrl       0x0017   /* 1  */
#define lt_ch_headph_ctrl    0x0079   /* 2  */
#define rt_ch_headph_ctrl    0x0079   /* 3  */
#define alog_au_path_ctrl    0x0000   /* 4  */
#define digi_au_path_ctrl    0x0000   /* 5  */
#define pow_mgt_ctrl_ctrl    0x0002   /* 6  */
#define digi_au_intf_ctrl    0x000D   /* 7  */
#define au_FS_TIM_ctrl       0x0000   /* 8 MCLK=12MHz, Sample Rate setting */
#define digi_intf1_ctrl      0x0001   /* 9  */
#define digi_intf2_ctrl      0x00FF   /* 10 */

#define DIGIF_FMT_MS              0x40
#define DIGIF_FMT_LRSWAP          0x20
#define DIGIF_FMT_LRP             0x10
#define DIGIF_FMT_IWL             0x0c
#define DIGIF_FMT_FOR             0x03

#define DIGIF_FMT_IWL_16          0x00
#define DIGIF_FMT_IWL_20          0x04
#define DIGIF_FMT_IWL_24          0x08
#define DIGIF_FMT_IWL_32          0xc0

#define DIGIF_FMT_FOR_MSBRIGHT    0x00
#define DIGIF_FMT_FOR_MSLEFT      0x01
#define DIGIF_FMT_FOR_I2S         0x02
#define DIGIF_FMT_FOR_DSP         0x03

#define POWER_DEV                 0x80
#define POWER_CLK                 0x40
#define POWER_OSC                 0x20
#define POWER_OUT                 0x10
#define POWER_DAC                 0x08
#define POWER_ADC                 0x04
#define POWER_MIC                 0x02
#define POWER_LINE                0x01

#define SRC_CLKOUT                0x80
#define SRC_CLKIN                 0x40
#define SRC_SR                    0x3c
#define SRC_BOSR                  0x00
#define SRC_MO                    0x01

#define SRC_SR_44                 0x0c
#define SRC_SR_32                 0x18
#define SRC_SR_96                 0x1C

#define ANAPCTL_STA               0xc0
#define ANAPCTL_STE               0x20
#define ANAPCTL_DAC               0x10
#define ANAPCTL_BYP               0x08
#define ANAPCTL_INSEL             0x00
#define ANAPCTL_MICM              0x02
#define ANAPCTL_MICB              0x01   

#define DIGPCTL_DACM              0x08
#define DIGPCTL_DEEMP             0x06
#define DIGPCTL_ADCHP             0x01
#define DIGPCTL_DEEMP_DIS         0x00
#define DIGPCTL_DEEMP_32          0x02
#define DIGPCTL_DEEMP_44          0x04
#define DIGPCRL_DEEMP_48          0x06

#define DIGIFACT_ACT              0x01

#define LT_HP_CTL_LZC             0x80
#define RT_HP_CTL_RZC             0x80

void AIC23_Write(unsigned short regaddr, unsigned short data)
{
    unsigned char buf[2];
    buf[0] = regaddr;
    buf[1] = data;
    I2C_Write(I2C_AIC23_0, 2, buf);
    I2C_Write(I2C_AIC23_1, 2, buf);
}
void McBSP0_InitSlave()
{
    PC55XX_MCSP pMCBSP0 = (PC55XX_MCSP)C55XX_MSP0_ADDR;
   
    // Put the MCBSP in reset
    Write(pMCBSP0 -> spcr1, 0);
    Write(pMCBSP0 -> spcr2, 0);
      
    // Config frame parameters (32 bit, single phase, no delay)
    Write(pMCBSP0 -> xcr1, XWDLEN1_32);
    Write(pMCBSP0 -> xcr2, XPHASE_SINGLE | XDATDLY_0);
    Write(pMCBSP0 -> rcr1, RWDLEN1_32);
    Write(pMCBSP0 -> rcr2, RPHASE_SINGLE | RDATDLY_0);

    // Disable int frame generation and enable slave w/ext frame signals on FSX
    // Frame sync is active high, data clocked on rising edge of clkx
    Write(pMCBSP0 -> pcr, PCR_CLKXP);

    // Bring transmitter and receiver out of reset
    SetMask(pMCBSP0 -> spcr2, SPCR2_XRST);
    SetMask(pMCBSP0 -> spcr1, SPCR1_RRST);   
}

void McBSP1_InitSlave()
{
    PC55XX_MCSP pMCBSP1 = (PC55XX_MCSP)C55XX_MSP1_ADDR;
   
    // Put the MCBSP in reset
    Write(pMCBSP1 -> spcr1, 0);
    Write(pMCBSP1 -> spcr2, 0);
      
    // Config frame parameters (32 bit, single phase, no delay)
    Write(pMCBSP1 -> xcr1, XWDLEN1_32);
    Write(pMCBSP1 -> xcr2, XPHASE_SINGLE | XDATDLY_0);
    Write(pMCBSP1 -> rcr1, RWDLEN1_32);
    Write(pMCBSP1 -> rcr2, RPHASE_SINGLE | RDATDLY_0);

    // Disable int frame generation and enable slave w/ext frame signals on FSX
    // Frame sync is active high, data clocked on rising edge of clkx
    Write(pMCBSP1 -> pcr, PCR_CLKXP);

    // Bring transmitter and receiver out of reset
    SetMask(pMCBSP1 -> spcr2, SPCR2_XRST);
    SetMask(pMCBSP1 -> spcr1, SPCR1_RRST);   
}
void AIC23_Init()
{
    I2C_Init();
   
    // Reset the AIC23 and turn on all power
    AIC23_Write(AIC23_RESET_REG, 0);
    AIC23_Write(AIC23_POWER_DOWN_CTL, 0);   
    AIC23_Write(AIC23_ANALOG_AUDIO_CTL,  0x10);
    AIC23_Write(AIC23_DIGITAL_AUDIO_CTL, 0);
   
    // Turn on volume for line inputs
    AIC23_Write(AIC23_LT_LINE_CTL,0x16);
    AIC23_Write(AIC23_RT_LINE_CTL,0x16);

    // Configure the AIC23 for master mode, 8KHz stereo, 16 bit samples
    // Use 12MHz USB clock
    AIC23_Write(AIC23_DIGITAL_IF_FORMAT, DIGIF_FMT_MS | DIGIF_FMT_IWL_16 | DIGIF_FMT_FOR_DSP);
    AIC23_Write(AIC23_SAMPLE_RATE_CTL, SRC_SR_32 | SRC_BOSR | SRC_MO);

    // Turn on headphone volume and digital interface
    AIC23_Write(AIC23_LT_HP_CTL, 0x078);  // 0x79 for speakers
    AIC23_Write(AIC23_RT_HP_CTL, 0x078);
    AIC23_Write(AIC23_DIG_IF_ACTIVATE, DIGIFACT_ACT);

    // Set McBSP0 to be transmit slave
    McBSP0_InitSlave();
    McBSP1_InitSlave();
}
void AIC23_Disable()
{
    PC55XX_MCSP pMCBSP0 = (PC55XX_MCSP)C55XX_MSP0_ADDR;
    I2C_Disable();
   
    // Put the MCBSP in reset
    Write(pMCBSP0 -> spcr1, 0);
    Write(pMCBSP0 -> spcr2, 0);
}
下面是I2C.c
#include "5509.h"
#include "util.h"
extern DSPCLK dspclk;
I2C_Init()
{
    PC55XX_I2C pI2C = (PC55XX_I2C)C55XX_I2C_ADDR;

    // Put I2C controller in reset (bad if clock derivatives change out of reset)
    ClearMask(pI2C -> icmdr, ICMDR_IRS);
   
    // Set prescaler to generate 12MHz clock
    pI2C -> icpsc = dspclk.pllmult;
      
    // Setup clock control registers (100KHz clock out)
    Write(pI2C -> icclkl, 10);  // For 400KHz, use 47 for 100KHz
    Write(pI2C -> icclkh, 10);
        
    // Setup master and slave addresses
    WriteMask(pI2C -> icoar, ICOAR_OADDR, ICOAR_MASK_7);

    // Take I2C controller out of reset, put in master mode
    SetMask(pI2C -> icmdr, ICMDR_IRS | ICMDR_MST);
}

I2C_Disable()
{
    PC55XX_I2C pI2C = (PC55XX_I2C)C55XX_I2C_ADDR;

    // Put I2C controller in reset (bad if clock derivatives change out of reset)
    ClearMask(pI2C -> icmdr, ICMDR_IRS);   
}

void I2C_Write(unsigned short int device, int count, unsigned char *bytedata)
{
    PC55XX_I2C pI2C = (PC55XX_I2C)C55XX_I2C_ADDR;
    int i;
        
    // Set the I2C controller to write a stream of count bytes
    Write(pI2C -> iccnt, count);
    WriteMask(pI2C -> icsar, device, ICSAR_MASK_7);
    WriteMask(pI2C -> icmdr,
        ICMDR_STT | ICMDR_STP | ICMDR_TRX,
        ICMDR_STT | ICMDR_STP | ICMDR_TRX);
        
    // Transmit data
    for (i = 0; i < count ; i++) {
        Write(pI2C -> icdxr, bytedata);
                while(!(pI2C -> icstr & ICSTR_ICXRDY));
    }
}



void I2C_Read(unsigned short int device, int count, unsigned char *bytedata)
{
    PC55XX_I2C pI2C = (PC55XX_I2C)C55XX_I2C_ADDR;
    int i;
      
    // Set the I2C controller to read a stream of count bytes
    Write(pI2C -> iccnt, count);
    WriteMask(pI2C -> icsar, device, ICSAR_MASK_7);
    WriteMask(pI2C -> icmdr,
        ICMDR_STT | ICMDR_STP,
        ICMDR_STT | ICMDR_STP | ICMDR_TRX);
   
    // Receive the data
    for (i = 0; i < count; i++)
    {
        // Wait for receive data to come back   
        while(!(pI2C -> icstr & ICSTR_ICRRDY));

        // Copy the data out
        bytedata = pI2C -> icdrr;
    }
}
下面是SDRAM_init.c
void SDRAM_init( void )
{      
    ioport unsigned int *ebsr  =(unsigned int *)0x6c00;
    ioport unsigned int *egcr  =(unsigned int *)0x800;
    ioport unsigned int *emirst=(unsigned int *)0x801;
    //ioport unsigned int *emibe =(unsigned int *)0x802;  
    ioport unsigned int *ce01  =(unsigned int *)0x803;
    //ioport unsigned int *ce02  =(unsigned int *)0x804;
    //ioport unsigned int *ce03  =(unsigned int *)0x805;
    ioport unsigned int *ce11  =(unsigned int *)0x806;
    //ioport unsigned int *ce12  =(unsigned int *)0x807;
    //ioport unsigned int *ce13  =(unsigned int *)0x808;
    ioport unsigned int *ce21  =(unsigned int *)0x809;
    //ioport unsigned int *ce22  =(unsigned int *)0x80A;
    //ioport unsigned int *ce23  =(unsigned int *)0x80B;
    ioport unsigned int *ce31  =(unsigned int *)0x80C;
    //ioport unsigned int *ce32  =(unsigned int *)0x80D;
    //ioport unsigned int *ce33  =(unsigned int *)0x80E;
    ioport unsigned int *sdc1  =(unsigned int *)0x80F;
    //ioport unsigned int *sdper =(unsigned int *)0x810;
    //ioport unsigned int *sdcnt =(unsigned int *)0x811;
    ioport unsigned int *init  =(unsigned int *)0x812;
    ioport unsigned int *sdc2  =(unsigned int *)0x813;
    *ebsr   = 0x221;//0xa01
    *egcr   = 0x200;
    *egcr   = 0X220;
    *ce01   = 0X3000;
    *ce11   = 0X3fff;
    *ce21   = 0x1fff;
    *ce31   = 0x1000;
    *emirst = 0;
    *sdc1   = 0X5958;
    *sdc2   = 0X38F;
    *init   = 0;
}     
下面是util.c
#include "5509.h"
#include "util.h"

DSPCLK dspclk;

void PLL_Init(int freq)
{
    PC55XX_CMOD pCMOD = (PC55XX_CMOD)C55XX_CLKMD_ADDR;

    // Calculate PLL multiplier values (only integral multiples now)
    dspclk.clkin = DSP_CLKIN;
    dspclk.pllmult = freq / dspclk.clkin;
    dspclk.freq = dspclk.pllmult * dspclk.clkin;
    dspclk.plldiv = 0;
    dspclk.nullloopclk = NULLLOOP_CLK;

    // Turn the PLL off
    ClearMask(pCMOD -> clkmd, CLKMD_PLLENABLE);
    while(ReadMask(pCMOD -> clkmd, CLKMD_LOCK));

    // Initialize PLL flags
    ClearMask(pCMOD -> clkmd, CLKMD_IAI);//0x4000
    SetMask(pCMOD -> clkmd, CLKMD_IOB | CLKMD_BREAKLN);//0x2000|0x0002

    // Set the multiplier/divisor
    WriteMask(pCMOD -> clkmd,
        CLKMD_PLLDIV_1 | CLKMD_BYPASSDIV_1,
        CLKMD_PLLDIV_MASK | CLKMD_BYPASSDIV_MASK);//0|0|
    WriteField(pCMOD -> clkmd, dspclk.pllmult, CLKMD_PLLMULT_MASK);

    // Enable the PLL and wait for lock
    SetMask(pCMOD -> clkmd, CLKMD_PLLENABLE);
    while(!ReadMask(pCMOD -> clkmd, CLKMD_LOCK));
}

void SWDelayUsec(unsigned int usec)
{
    unsigned int i, j, loopsperusec;

    loopsperusec = dspclk.freq / dspclk.nullloopclk;
    for (i=0;i         for (j = 0; j < loopsperusec; j++);
}

void SWDelayMsec(unsigned int msec)
{
    unsigned int i;
    for (i=0;i         SWDelayUsec(1000);
}

int firstbit(unsigned short mask)
{
    int shiftamt;
    unsigned short bit;

    // Find offset of first bit in mask
    bit = 1;
    for (shiftamt = 0; shiftamt < 16; shiftamt++) {
        if (bit & mask)
            break;
        bit = bit << 1;
    }

    return shiftamt;
}
希望大神能看下哪有问题

zhaironghui

自己做的板子吗？看着像是 DSP 的 JTAG 下载线受到了干扰，如果是自己做的板子，可以看看 PCB 上是不是有的线（特别是时钟线）离 JTAG 太近了，导致了干扰。

陌上花开zl

zhaironghui 发表于 2016-1-12 16:03
自己做的板子吗？看着像是 DSP 的 JTAG 下载线受到了干扰，如果是自己做的板子，可以看看 PCB 上是不是有的 ...

谢谢大神的回复，之前的问题解决了，是仿真器的问题，现在好了，不知大神能否帮我看下主程序，单步运行时进不了中断程序，因为一直进入不了中断程序，所以程序一直停在    if(TIME_flag==1)这句函数
void interrupt Timer()
{
        TIME_flag=1;
        count_timer++;
}，希望大神能指导下大概什么原因？

ailika6615

你这个仿真器的问题怎么解决的？