Cortex-M3 AT520 RTL Validation

gxliu08

Cortex-M3 AT520 RTL Validation [复制链接]

Loading val_report.cfg
###########################################################################################
# SANDCAT Validation Report for logs #
# ------------------------------------------ #
# #
# Version: 1.314 #
# Command: val_report cortex-m3_ETM.list -vcs #
# Model: CM3_r2p0_00rel0 #
# #
###########################################################################################

*****************************************************************************************************************
* SANDCAT (native) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
sc_hellow PASSED OK 10334 00rel0 214 0:00:08 Jun 24 10:17
sc_info PASSED OK 25957 00rel0 711 0:00:10 Jun 24 10:17

TOTAL: 2 2 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 925, CPU = 0:00:01, REAL = 0:00:18

*****************************************************************************************************************
* TN_MPU (sc_systick.sc_waitstate) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
tn_mpu_2rgn_srd PASSED OK 10333 00rel0 80020 0:00:50 Jun 24 10:18
tn_mpu_bm_cov1 PASSED OK 10333 00rel0 26884 0:00:26 Jun 24 10:18
tn_mpu_reg_user PASSED OK 10333 00rel0 447295 0:03:28 Jun 24 10:21
tn_mpu_srd_16MB PASSED OK 10333 00rel0 70805 0:00:40 Jun 24 10:18
tn_mpu_srd_1GB PASSED OK 10333 00rel0 125502 0:01:08 Jun 24 10:19
tn_mpu_srd_1KB PASSED OK 10333 00rel0 90220 0:00:56 Jun 24 10:19
tn_mpu_srd_1MB PASSED OK 10333 00rel0 72326 0:00:54 Jun 24 10:19
tn_mpu_srd_256B PASSED OK 10333 00rel0 79033 0:00:55 Jun 24 10:19
tn_mpu_srd_256KB PASSED OK 10333 00rel0 70181 0:00:58 Jun 24 10:19
tn_mpu_srd_256MB PASSED OK 10333 00rel0 68461 0:00:57 Jun 24 10:19
tn_mpu_srd_2GB PASSED OK 10333 00rel0 96181 0:00:59 Jun 24 10:19
tn_mpu_srd_2MB PASSED OK 10333 00rel0 69052 0:00:58 Jun 24 10:19
tn_mpu_srd_32MB PASSED OK 10333 00rel0 100003 0:00:53 Jun 24 10:19
tn_mpu_srd_4MB PASSED OK 10333 00rel0 69052 0:00:45 Jun 24 10:19
tn_mpu_srd_512KB PASSED OK 10333 00rel0 71739 0:00:45 Jun 24 10:19
tn_mpu_srd_64MB PASSED OK 10333 00rel0 69858 0:00:45 Jun 24 10:19
tn_mpu_srd_8MB PASSED OK 10333 00rel0 70181 0:00:48 Jun 24 10:19
tn_mpu_srd_test PASSED OK 10333 00rel0 43674 0:00:33 Jun 24 10:19
tn_mpu_unalign_acc PASSED OK 10333 00rel0 86555 0:00:53 Jun 24 10:19
tn_mpu_unalign_hw_ldrsb PASSED OK 10333 00rel0 31364 0:00:29 Jun 24 10:18

TOTAL: 20 20 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 1838386, CPU = 0:14:03, REAL = 0:19:00

*****************************************************************************************************************
* TN_MPU (sc_hwstep) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
tn_mpu_mem_attr_128B PASSED OK 10333 00rel0 159169 0:00:43 Jun 24 10:19
tn_mpu_mem_attr_2rgn3 PASSED OK 10333 00rel0 195601 0:00:51 Jun 24 10:19
tn_mpu_misc PASSED OK 10333 00rel0 107685 0:00:30 Jun 24 10:18
tn_mpu_misc_cover PASSED OK 10333 00rel0 41949 0:00:15 Jun 24 10:18
tn_mpu_off_chk PASSED OK 10333 00rel0 93772 0:00:53 Jun 24 10:19
tn_mpu_pri_flt PASSED OK 10333 00rel0 120753 0:00:59 Jun 24 10:19
tn_mpu_srd_128MB PASSED OK 10333 00rel0 111249 0:00:57 Jun 24 10:19
tn_mpu_srd_16KB PASSED OK 10333 00rel0 269657 0:01:34 Jun 24 10:20
tn_mpu_srd_1KB PASSED OK 10333 00rel0 144913 0:01:04 Jun 24 10:19
tn_mpu_srd_4KB PASSED OK 10333 00rel0 133429 0:01:01 Jun 24 10:19
tn_mpu_srd_512B PASSED OK 10333 00rel0 135409 0:01:01 Jun 24 10:19
tn_mpu_srd_512MB PASSED OK 10333 00rel0 110853 0:00:56 Jun 24 10:19

TOTAL: 12 12 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 1624439, CPU = 0:06:26, REAL = 0:10:44

*****************************************************************************************************************
* CM3_DBG (sc_waitstate) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
cm3_dbg_DWT_PCSAMPLE_SLEEPING PASSED OK 7280 00rel0 1452 0:00:29 Jun 24 10:19
cm3_dbg_DWT_SAMPLESTATU PASSED OK 3633 00rel0 3000 0:00:30 Jun 24 10:19
cm3_dbg_VECTCLRACTIVE PASSED OK 18507 00rel0 1124 0:00:29 Jun 24 10:19
cm3_dbg_catInterr_stacking PASSED OK 20302 00rel0 919 0:00:29 Jun 24 10:19
sc_debug_itm_swv_tpm PASSED OK 7657 00rel0 2517 0:00:17 Jun 24 10:19
sc_debug_itm_ts_overflow PASSED OK 18507 00rel0 3404 0:00:17 Jun 24 10:19
sc_debug_jtag_sleep_sp PASSED OK 10327 00rel0 6642 0:00:18 Jun 24 10:19
sc_debug_swd_abort PASSED OK 26228 00rel0 1764 0:00:15 Jun 24 10:19
sc_debug_swd_nconterr PASSED OK 18507 00rel0 1920 0:00:27 Jun 24 10:19

TOTAL: 9 9 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 22742, CPU = 0:00:16, REAL = 0:03:31

*****************************************************************************************************************
* CM3_DBG (sc_systick) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
cm3_dbg_DWT_SAMPLESTATU PASSED OK 3633 00rel0 13786 0:00:36 Jun 24 10:19
sc_debug_dwt_matched_etm_r PASSED OK 7614 00rel0 19654 0:00:40 Jun 24 10:19

TOTAL: 2 2 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 33440, CPU = 0:00:22, REAL = 0:01:16

*****************************************************************************************************************
* CM3_DBG (sc_systick.sc_waitstate) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
cm3_dbg_DWT_ADDRMASKRANGE PASSED OK 18507 00rel0 19062 0:00:36 Jun 24 10:19
cm3_dbg_DWT_CPIEVT PASSED OK 18507 00rel0 25936 0:00:47 Jun 24 10:19
cm3_dbg_DWT_FOLD_LSUEVT PASSED OK 18507 00rel0 22215 0:00:43 Jun 24 10:19
cm3_dbg_DWT_FUNC1_BEFBUSFLT PASSED OK 18507 00rel0 32250 0:00:45 Jun 24 10:19
cm3_dbg_DWT_FUNC2_BEFMEMMGMT PASSED OK 18507 00rel0 58228 0:00:57 Jun 24 10:19
cm3_dbg_DWT_FUNC3_BEFUSAGE PASSED OK 18507 00rel0 58337 0:00:36 Jun 24 10:19
cm3_dbg_DWT_FUNC3_MEMMGMT PASSED OK 18507 00rel0 56919 0:00:35 Jun 24 10:19
cm3_dbg_DWT_INTEVT PASSED OK 18507 00rel0 27565 0:00:27 Jun 24 10:19
cm3_dbg_DWT_MASK7 PASSED OK 18507 00rel0 17176 0:00:17 Jun 24 10:19
cm3_dbg_DWT_MASKF PASSED OK 18507 00rel0 16992 0:00:37 Jun 24 10:19
cm3_dbg_DWT_MASKLSB PASSED OK 18507 00rel0 18223 0:00:38 Jun 24 10:19
cm3_dbg_DWT_PCSAMPLENA PASSED OK 18507 00rel0 17735 0:00:39 Jun 24 10:19
cm3_dbg_DWT_SAMPLESTATU PASSED OK 3633 00rel0 23821 0:00:43 Jun 24 10:19
cm3_dbg_DWT_SMPLEPC_PSCNTMATCH PASSED OK 18507 00rel0 19151 0:00:21 Jun 24 10:19
cm3_dbg_DWT_SNYCTAP2 PASSED OK 18507 00rel0 12545 0:00:18 Jun 24 10:19
cm3_dbg_DWT_STOP_PCMATCH PASSED OK 18507 00rel0 18527 0:00:19 Jun 24 10:19
cm3_dbg_DWT_SYNCTAP3 PASSED OK 18507 00rel0 12545 0:00:18 Jun 24 10:19
cm3_dbg_DWT_WPSMPLPCDATA_EVENT PASSED OK 18507 00rel0 23374 0:00:48 Jun 24 10:19
cm3_dbg_ROMTABLE_WRITE PASSED OK 21325 00rel0 116350 0:02:02 Jun 24 10:20
cm3_dbg_Rmacro PASSED OK 18507 00rel0 16003 0:00:42 Jun 24 10:19
cm3_dbg_USERMODE_DWT_REGACCESS PASSED OK 18507 00rel0 11567 0:00:40 Jun 24 10:19
sc_debug_dap_auto_inc PASSED OK 7280 00rel0 11046 0:00:35 Jun 24 10:19
sc_debug_dap_resrv PASSED OK 7280 00rel0 16220 0:00:37 Jun 24 10:19
sc_debug_dwt_datamatch_w_wp PASSED OK 7614 00rel0 48391 0:00:53 Jun 24 10:19
sc_debug_dwt_datav_hw_transize_w_r_wp2 PASSED OK 7614 00rel0 65736 0:01:00 Jun 24 10:19
sc_debug_dwt_datav_hw_transize_w_r_wp3 PASSED OK 7614 00rel0 73994 0:00:45 Jun 24 10:19
sc_debug_dwt_datav_w_transize_w_r_wp2 PASSED OK 7614 00rel0 38362 0:00:29 Jun 24 10:19
sc_debug_dwt_matched_etm_r PASSED OK 7614 00rel0 31633 0:00:32 Jun 24 10:19
sc_debug_fpb_instr_remap_edev PASSED OK 18507 00rel0 21914 0:00:23 Jun 24 10:19
sc_debug_fpb_reg PASSED OK 18507 00rel0 31333 0:00:30 Jun 24 10:19
sc_debug_itm_reg PASSED OK 18507 00rel0 32775 0:00:32 Jun 24 10:19
sc_debug_itm_tpm PASSED OK 18507 00rel0 24753 0:00:29 Jun 24 10:19
sc_debug_itm_uart PASSED OK 18507 00rel0 26112 0:00:30 Jun 24 10:19
sc_debug_jtag_dwt_cpievt PASSED OK 18507 00rel0 37676 0:00:30 Jun 24 10:19
sc_debug_jtag_dwt_cycevt PASSED OK 18507 00rel0 40949 0:00:30 Jun 24 10:19
sc_debug_jtag_dwt_intevt PASSED OK 18507 00rel0 41517 0:00:33 Jun 24 10:19
sc_debug_jtag_fault_staterr_mmerr_fpb PASSED OK 18507 00rel0 121002 0:01:24 Jun 24 10:20
sc_debug_jtag_fpb_instr_remap PASSED OK 18507 00rel0 34408 0:00:48 Jun 24 10:19
sc_debug_jtag_itm_integration PASSED OK 18507 00rel0 45353 0:00:52 Jun 24 10:19
sc_debug_jtag_itm_sync PASSED OK 18507 00rel0 51952 0:00:58 Jun 24 10:19
sc_debug_jtag_nconterr PASSED OK 10327 00rel0 24275 0:00:44 Jun 24 10:19
sc_debug_jtag_rw PASSED OK 26113 00rel0 31063 0:00:48 Jun 24 10:19
sc_debug_jtag_trncnt_pv PASSED OK 7280 00rel0 44387 0:00:58 Jun 24 10:19
sc_debug_lockup_snapstall PASSED OK 18507 00rel0 16307 0:00:38 Jun 24 10:19
sc_debug_swd_err PASSED OK 18507 00rel0 39859 0:00:58 Jun 24 10:19
sc_debug_swd_fpb_instr_remap PASSED OK 18507 00rel0 41022 0:00:53 Jun 24 10:19
sc_debug_swd_itm_usr PASSED OK 18507 00rel0 110412 0:01:26 Jun 24 10:20
sc_debug_swd_rom PASSED OK 7280 00rel0 25575 0:00:49 Jun 24 10:19
sc_debug_swd_rw PASSED OK 18507 00rel0 42479 0:00:50 Jun 24 10:19
sc_debug_swd_trncnt_pv PASSED OK 7280 00rel0 45587 0:00:52 Jun 24 10:19
sc_debug_swd_turn PASSED OK 18507 00rel0 53843 0:00:57 Jun 24 10:19
sc_debug_unalign_dap PASSED OK 21009 00rel0 48148 0:00:46 Jun 24 10:19

TOTAL: 52 52 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 1942604, CPU = 0:18:26, REAL = 0:37:17

*****************************************************************************************************************
* CM3_DBG (native) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
sc_debug_itm_ts_prescale01 PASSED OK 23986 00rel0 1773 0:00:09 Jun 24 10:18
sc_debug_itm_ts_prescale10 PASSED OK 23986 00rel0 1771 0:00:09 Jun 24 10:18
sc_debug_itm_ts_prescale11 PASSED OK 23986 00rel0 1669 0:00:08 Jun 24 10:18
sc_debug_jtag_abort PASSED OK 25166 00rel0 2645 0:00:09 Jun 24 10:18

TOTAL: 4 4 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 7858, CPU = 0:00:07, REAL = 0:00:35

*****************************************************************************************************************
* CM3_NVIC (sc_systick.sc_waitstate) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
cm3_nvic_designerconcern_4 PASSED OK 18509 00rel0 50494 0:00:34 Jun 24 10:19
cm3_nvic_designerconcern_8 PASSED OK 18509 00rel0 89371 0:01:02 Jun 24 10:19
cm3_nvic_designerconcern_dap_unalign PASSED OK 18509 00rel0 32275 0:00:32 Jun 24 10:19
cm3_nvic_designerconcern_dapen PASSED OK 18509 00rel0 19145 0:00:18 Jun 24 10:19
cm3_nvic_designerconcern_fault_at_reset PASSED OK 18509 00rel0 27887 0:00:42 Jun 24 10:19
cm3_nvic_iflush_test1 PASSED OK 10340 00rel0 67508 0:00:48 Jun 24 10:19

TOTAL: 6 6 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 286680, CPU = 0:02:26, REAL = 0:03:56

*****************************************************************************************************************
* CM3_NVIC (sc_waitstate) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
cm3_nvic_designerconcern_5 PASSED OK 18509 00rel0 6475 0:00:32 Jun 24 10:19
cm3_nvic_designerconcern_dapapsel PASSED OK 18509 00rel0 857 0:00:15 Jun 24 10:19
cm3_nvic_sys_autovect PASSED OK 23921 00rel0 14206 0:00:22 Jun 24 10:19

TOTAL: 3 3 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 21538, CPU = 0:00:11, REAL = 0:01:09

*****************************************************************************************************************
* CM3_NVIC (sc_hwstep) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
cm3_nvic_designerconcern_1 PASSED OK 19041 00rel0 123974 0:00:44 Jun 24 10:20
cm3_nvic_fault_at_exception PASSED OK 18509 00rel0 34425 0:00:24 Jun 24 10:19
cm3_nvic_masks PASSED OK 18509 00rel0 208220 0:00:57 Jun 24 10:20

TOTAL: 3 3 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 366619, CPU = 0:01:26, REAL = 0:02:05

*****************************************************************************************************************
* CM3_NVIC (sc_monstep) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
cm3_nvic_irq_pending PASSED OK 10328 00rel0 10971 0:00:14 Jun 24 10:19
cm3_nvic_regtest PASSED OK 18509 00rel0 267693 0:02:31 Jun 24 10:21

TOTAL: 2 2 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 278664, CPU = 0:02:28, REAL = 0:02:45

*****************************************************************************************************************
* CM3_NVIC (native) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
cm3_nvic_allirq_t7 PASSED OK 18509 00rel0 1840 0:00:08 Jun 24 10:19
cm3_nvic_designerconcern_6 PASSED OK 18509 00rel0 4259 0:00:11 Jun 24 10:19
cm3_nvic_irq_lr_corner_case PASSED OK 18509 00rel0 8115 0:00:12 Jun 24 10:19
cm3_nvic_multicyc_inst_waitstates PASSED OK 18509 00rel0 113660 0:00:51 Jun 24 10:20
cm3_nvic_simultaneous_fault PASSED OK 10328 00rel0 1378 0:00:09 Jun 24 10:19
cm3_nvic_wfi_wfe PASSED OK 26272 00rel0 20284 0:00:25 Jun 24 10:19

TOTAL: 6 6 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 149536, CPU = 0:01:08, REAL = 0:01:56

*****************************************************************************************************************
* TN_DEBUG (sc_systick.sc_waitstate) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
tndebug_dap_bank1 PASSED OK 18514 00rel0 26605 0:00:24 Jun 24 10:19
tndebug_dap_err PASSED OK 18514 00rel0 89908 0:01:05 Jun 24 10:20
tndebug_dap_packed_read PASSED OK 18514 00rel0 246553 0:02:18 Jun 24 10:21
tndebug_dap_packed_writes PASSED OK 18514 00rel0 246566 0:02:28 Jun 24 10:21
tndebug_dap_reset PASSED OK 21070 00rel0 10503 0:00:25 Jun 24 10:19
tndebug_dap_simultaccess_2 PASSED OK 18514 00rel0 45985 0:00:53 Jun 24 10:20
tndebug_dwt_in_exception_1_sample_pc_data PASSED OK 20788 00rel0 44932 0:00:41 Jun 24 10:19
tndebug_dwt_mem_type_LS_3 PASSED OK 20788 00rel0 192649 0:01:51 Jun 24 10:21
tndebug_dwt_mem_type_sample_pc_data PASSED OK 20788 00rel0 444417 0:03:39 Jun 24 10:23
tndebug_dwt_simple_sample_pc_data PASSED OK 20788 00rel0 609001 0:04:49 Jun 24 10:24
tndebug_fpb_literal_2 PASSED OK 18514 00rel0 22830 0:00:30 Jun 24 10:20
tndebug_fpb_misc_1 PASSED OK 18514 00rel0 183470 0:01:41 Jun 24 10:21
tndebug_fpb_nobpt PASSED OK 20788 00rel0 26826 0:00:32 Jun 24 10:20
tndebug_hw_mem_read_1 PASSED OK 18514 00rel0 96729 0:01:02 Jun 24 10:20
tndebug_rom_table_1 PASSED OK 18514 00rel0 54927 0:00:45 Jun 24 10:20

TOTAL: 15 15 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 2341901, CPU = 0:18:40, REAL = 0:23:03

*****************************************************************************************************************
* TN_DEBUG (sc_waitstate) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
tndebug_fpb_literal_6 PASSED OK 18514 00rel0 5292 0:00:12 Jun 24 10:20

TOTAL: 1 1 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 5292, CPU = 0:00:03, REAL = 0:00:12

*****************************************************************************************************************
* TN_DEBUG (native) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
tndebug_sw_step_over_instr_DP_4 PASSED OK 20788 00rel0 81748 0:00:55 Jun 24 10:20

TOTAL: 1 1 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 81748, CPU = 0:00:47, REAL = 0:00:55

*****************************************************************************************************************
* TN_ARCH (sc_systick.sc_waitstate) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
tn_arch_core_epsr_BacktoBack_P2 PASSED OK 20789 00rel0 36509 0:00:27 Jun 24 10:20
tn_arch_core_single_LSM_in_IT_p1 PASSED OK 20789 00rel0 469379 0:03:33 Jun 24 10:23
tn_arch_nvic_sbz_bits_1 PASSED OK 10330 00rel0 472045 0:03:40 Jun 24 10:23
tn_arch_priv_entr_base_act_p1 PASSED OK 20789 00rel0 32361 0:00:24 Jun 24 10:20

TOTAL: 4 4 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 1010294, CPU = 0:07:26, REAL = 0:08:04

*****************************************************************************************************************
* TN_ARCH (sc_waitstate) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
tn_arch_nvic_sbz_bits PASSED OK 20789 00rel0 123671 0:01:05 Jun 24 10:20

TOTAL: 1 1 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 123671, CPU = 0:00:56, REAL = 0:01:05

*****************************************************************************************************************
* TN_ARCH (sc_hwstep) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
tn_arch_nvic_readonly_bits PASSED OK 20789 00rel0 128677 0:00:39 Jun 24 10:20

TOTAL: 1 1 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 128677, CPU = 0:00:30, REAL = 0:00:39

*****************************************************************************************************************
* CM3_MEM (sc_systick.sc_waitstate) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
ALU_332_CONDCOV PASSED OK 7287 00rel0 7997 0:00:18 Jun 24 10:20
LSU_352_CONDCOVMPU PASSED OK 4051 00rel0 8019 0:00:18 Jun 24 10:20
NVIC_886_CONDCOV PASSED OK 7280 00rel0 25986 0:00:28 Jun 24 10:20
cm3_et_dc PASSED OK 10329 00rel0 430157 0:03:27 Jun 24 10:23
cm3_mpu_iside_overlap PASSED OK 10329 00rel0 42558 0:00:39 Jun 24 10:20
cm3_mpu_reg_misc PASSED OK 10329 00rel0 14114 0:00:26 Jun 24 10:20
cm3_mpu_srd_64B PASSED OK 10329 00rel0 106228 0:01:07 Jun 24 10:21
cm3_tn_mem_ul_brb PASSED OK 10329 00rel0 8709 0:00:22 Jun 24 10:20

TOTAL: 8 8 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 643768, CPU = 0:04:51, REAL = 0:07:05

*****************************************************************************************************************
* CM3_MEM (sc_hwstep) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
cm3_mpu_rgn_size PASSED OK 10329 00rel0 70857 0:00:25 Jun 24 10:20
cm3_mpu_srd_32B PASSED OK 10329 00rel0 186097 0:00:51 Jun 24 10:21

TOTAL: 2 2 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 256954, CPU = 0:01:00, REAL = 0:01:16

*****************************************************************************************************************
* TN_ISA (sc_systick.sc_waitstate) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
tnt1_ls_STM_p1 PASSED OK 10332 00rel0 23748 0:00:21 Jun 24 10:20
tnt2_br_ADD_pc PASSED OK 10332 00rel0 106758 0:00:58 Jun 24 10:21
tnt2_br_TBB_p0 PASSED OK 10332 00rel0 80869 0:00:51 Jun 24 10:21
tnt2_co_BtoB PASSED OK 10332 00rel0 243458 0:02:03 Jun 24 10:22
tnt2_co_IT_p3 PASSED OK 10332 00rel0 56767 0:00:41 Jun 24 10:21
tnt2_dp_AND_p2 PASSED OK 10332 00rel0 169137 0:01:24 Jun 24 10:21
tnt2_dp_CMP_p0 PASSED OK 10332 00rel0 244246 0:01:57 Jun 24 10:22
tnt2_dp_ORN_p1 PASSED OK 10332 00rel0 140817 0:01:13 Jun 24 10:21
tnt2_dp_ORR_p1 PASSED OK 10332 00rel0 133344 0:01:10 Jun 24 10:21

TOTAL: 9 9 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 1199144, CPU = 0:09:00, REAL = 0:10:38

*****************************************************************************************************************
* TN_ISA (sc_hwstep) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
tnt2_dp_USAT_p0 PASSED OK 10336 00rel0 229657 0:01:04 Jun 24 10:21

TOTAL: 1 1 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 229657, CPU = 0:00:53, REAL = 0:01:04

*****************************************************************************************************************
* CM3_WIC (sc_waitstate) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
cm3_wic_irq PASSED OK 26208 00rel0 5347 0:00:15 Jun 24 10:20
cm3_wic_nmi PASSED OK 26180 00rel0 1179 0:00:12 Jun 24 10:20
cm3_wic_simple PASSED OK 26173 00rel0 2666 0:00:13 Jun 24 10:20
cm3_wic_sleeponexit PASSED OK 26217 00rel0 2278 0:00:07 Jun 24 10:20
cm3_wic_wakeup_priority_1 PASSED OK 26190 00rel0 2873 0:00:09 Jun 24 10:21

TOTAL: 5 5 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 14343, CPU = 0:00:10, REAL = 0:00:56

*****************************************************************************************************************
* CM3_WIC (native) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
cm3_wic_disable_1 PASSED OK 26180 00rel0 810 0:00:08 Jun 24 10:21
cm3_wic_mask_change_bf_sleep PASSED OK 26341 00rel0 3103 0:00:11 Jun 24 10:21
cm3_wic_mpu_mem PASSED OK 26223 00rel0 5328 0:00:11 Jun 24 10:21
cm3_wic_pulse_edbgrq_timing_corner PASSED OK 26183 00rel0 1892 0:00:08 Jun 24 10:21
cm3_wic_rxev PASSED OK 26205 00rel0 1413 0:00:06 Jun 24 10:21

TOTAL: 5 5 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 12546, CPU = 0:00:09, REAL = 0:00:44

*****************************************************************************************************************
* CM3_ERRATA (native) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
cm3_errata_368884 PASSED OK 9998 00rel0 162 0:00:05 Jun 24 10:21
cm3_errata_369016 PASSED OK 10228 00rel0 4093 0:00:09 Jun 24 10:21
cm3_errata_377489 PASSED OK 10312 00rel0 214 0:00:06 Jun 24 10:21
cm3_errata_377490 PASSED OK 10312 00rel0 3441 0:00:08 Jun 24 10:21
cm3_errata_377491 PASSED OK 10312 00rel0 408 0:00:06 Jun 24 10:21
cm3_errata_377492 PASSED OK 18510 00rel0 4962 0:00:10 Jun 24 10:21
cm3_errata_377493 PASSED OK 18510 00rel0 666 0:00:08 Jun 24 10:21
cm3_errata_377494 PASSED OK 10312 00rel0 114 0:00:09 Jun 24 10:21
cm3_errata_377495 PASSED OK 18510 00rel0 437 0:00:07 Jun 24 10:21
cm3_errata_377496 PASSED OK 10312 00rel0 6410 0:00:11 Jun 24 10:21
cm3_errata_377497 PASSED OK 18510 00rel0 716 0:00:06 Jun 24 10:21
cm3_errata_377498 PASSED OK 23856 00rel0 1945 0:00:07 Jun 24 10:21
cm3_errata_377499 PASSED OK 18510 00rel0 1804 0:00:06 Jun 24 10:21
cm3_errata_377519 PASSED OK 10312 00rel0 3864 0:00:08 Jun 24 10:21
cm3_errata_377521 PASSED OK 10312 00rel0 1531 0:00:09 Jun 24 10:21
cm3_errata_377522 PASSED OK 10312 00rel0 223 0:00:08 Jun 24 10:21
cm3_errata_377523 PASSED OK 18510 00rel0 454 0:00:09 Jun 24 10:21
cm3_errata_377681 PASSED OK 10312 00rel0 15596 0:00:17 Jun 24 10:21
cm3_errata_377985 PASSED OK 20790 00rel0 1076 0:00:11 Jun 24 10:21
cm3_errata_382856 PASSED OK 10312 00rel0 196 0:00:10 Jun 24 10:21
cm3_errata_382857 PASSED OK 10312 00rel0 212 0:00:10 Jun 24 10:21
cm3_errata_382858 PASSED OK 10312 00rel0 1558 0:00:11 Jun 24 10:21
cm3_errata_382859 PASSED OK 10312 00rel0 28986 0:00:25 Jun 24 10:22
cm3_errata_382860 PASSED OK 18510 00rel0 1084 0:00:08 Jun 24 10:21
cm3_errata_382861 PASSED OK 10312 00rel0 948 0:00:09 Jun 24 10:21
cm3_errata_382862 PASSED OK 10312 00rel0 2611 0:00:10 Jun 24 10:21
cm3_errata_429964 PASSED OK --- 00rel0 1500 0:00:08 Jun 24 10:21
cm3_errata_429965 PASSED OK --- 00rel0 38391 0:00:32 Jun 24 10:22
cm3_errata_DBGPWRUP PASSED OK --- 00rel0 1916 0:00:09 Jun 24 10:21
cm3_errata_STREX_EXIT PASSED OK 10625 00rel0 113 0:00:06 Jun 24 10:21
cm3_errata_UMULL PASSED OK 10624 00rel0 163 0:00:06 Jun 24 10:21
cm3_errata_dfsr_bkpt PASSED OK 22264 00rel0 1267 0:00:06 Jun 24 10:21
cm3_errata_dwt_cpicounter_sleep PASSED OK 25760 00rel0 728 0:00:06 Jun 24 10:21
cm3_errata_hprot_extppb PASSED OK 18510 00rel0 628 0:00:07 Jun 24 10:21
cm3_errata_ihprot_after_exc_return PASSED OK 24969 00rel0 404 0:00:03 Jun 24 10:22
cm3_errata_mpu_unaligned_fault PASSED OK 22264 00rel0 1198 0:00:04 Jun 24 10:22
cm3_errata_sleeponexit PASSED OK 22264 00rel0 626 0:00:03 Jun 24 10:22
cm3_errata_tpiu_formatterbypass PASSED OK 18510 00rel0 1585 0:00:04 Jun 24 10:22
cm3_errata_vendor_specific_be8 PASSED OK 23194 00rel0 212 0:00:05 Jun 24 10:22
cm3_errata_wfi_busfault PASSED OK 26251 00rel0 378 0:00:06 Jun 24 10:22

TOTAL: 40 40 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 132820, CPU = 0:01:28, REAL = 0:05:48

*****************************************************************************************************************
* ETMM3 (noetmTrc) TESTS *
*****************************************************************************************************************

TestName Result Rev Model Cycles Time Timestamp
---------------------------------------------------------------------------------------------------------
etmm3_ASyncTrig PASSED OK 24380 00rel0 884 0:00:06 Jun 24 10:22
etmm3_ID_reg_write PASSED OK 24372 00rel0 216 0:00:05 Jun 24 10:22
etmm3_Overflow PASSED OK 18511 00rel0 258 0:00:09 Jun 24 10:22
etmm3_Overflow_dbgentry PASSED OK 18511 00rel0 579 0:00:10 Jun 24 10:22
etmm3_Overflow_reprog PASSED OK 18511 00rel0 421 0:00:10 Jun 24 10:22
etmm3_TraceEn_at_isr_end PASSED OK 24380 00rel0 210 0:00:08 Jun 24 10:22
etmm3_integration_regs PASSED OK 20640 00rel0 2268 0:00:09 Jun 24 10:22
etmm3_multitrigger_dbgrq_1 PASSED OK 20646 00rel0 700 0:00:08 Jun 24 10:22
etmm3_multitrigger_dbgrq_2 PASSED OK 20645 00rel0 1002 0:00:08 Jun 24 10:22
etmm3_trigger_dbgrq PASSED OK 18511 00rel0 621 0:00:10 Jun 24 10:22

TOTAL: 10 10 PASSED, 0 FAILED, 0 ABANDONED, 0 NOT RUN
times: SIM = 7159, CPU = 0:00:06, REAL = 0:01:23

*********************************************
TOTAL TESTS : 224
TOTAL PASSED : 224
TOTAL CPU TIME : 1.56 hours
TOTAL REAL TIME : 2.46 hours
TOTAL CYCLES : 12761k
CYCLES PER SECOND : 2274
BATCH REAL TIME : 0.11
PARALLELISM : 21.52
*********************************************

AR010-DC-70005-r1p0-05rel0:

doc/
doc/ETM_architecture/
doc/ETM_architecture/IHI0014O_ETM_ArchSpec.pdf

AT420-DA-00001-r2p0-00rel0:

docs/
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docs/DDI0337G_cortex_m3_r2p0_trm/graphics/reset_signals.vsd
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docs/DDI0337G_cortex_m3_r2p0_trm/graphics/return_from_exception_packet_encoding_.vsd
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docs/DDI0337G_cortex_m3_r2p0_trm/graphics/return_from_interrupt_flowchart.vsd
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docs/DDI0337G_cortex_m3_r2p0_trm/graphics/sleeping_power_control_example.vsd
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docs/DDI0337G_cortex_m3_r2p0_trm/graphics/system_handler_priority_registers_bit_assignments.vsd
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docs/DDI0337G_cortex_m3_r2p0_trm/graphics/systick_reload_value_register_bit_assignments.vsd
docs/DDI0337G_cortex_m3_r2p0_trm/graphics/tail_chaining_timing.vsd
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docs/DDI0337G_cortex_m3_r2p0_trm/graphics/unconditional_branch_with_pipeline_stalls.vsd
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docs/DDI0337G_cortex_m3_r2p0_trm/graphics/usage_fault_status_register_bit_assignments.vsd
docs/DDI0337G_cortex_m3_r2p0_trm/graphics/vector_table_offset_register_bit_assignments.svg
docs/DDI0337G_cortex_m3_r2p0_trm/graphics/vector_table_offset_register_bit_assignments.vsd
docs/DDI0337G_cortex_m3_r2p0_trm/graphics/wic_mode_enable_sequence.svg
docs/DDI0337G_cortex_m3_r2p0_trm/graphics/wic_mode_enable_sequence.vsd
docs/DDI0337G_cortex_m3_r2p0_trm/readme.txt
docs/DDI0337G_cortex_m3_r2p0_trm/TMA_signal_descriptions.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_ac_characteristics.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_ahb_trace_macrocell_interface.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_bookinfo.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_bus_interface.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_clocking_and_resets.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_core_debug.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_debug_port.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_embedded_trace_macrocell.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_embedded_trace_macrocell_interface.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_exceptions.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_glossary.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_instruction_timing.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_introduction.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_memory_map.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_memory_protection_unit.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_nested_vectored_interrupt_controller.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_power_management.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_preface.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_programmers_model.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_system_control.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_system_debug.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TM_trace_port_interface_unit.fm
docs/DDI0337G_cortex_m3_r2p0_trm/TRM_revisions.fm

AT420-DA-03001-r2p0-00rel0:

docs/
docs/DDI0337G_cortex_m3_r2p0_trm.pdf

AT420-DC-02008-r2p0-00rel0:

docs/
docs/DII0194A_cortex_m3_r2p0_csg.pdf

AT420-DC-13001-r2p0-00rel0:

docs/
docs/DII0113E_cortex_m3_r2p0_im.pdf

AT420-DC-13002-r2p0-00rel0:

docs/
docs/DII0113E_cortex_m3_r2p0_im/
docs/DII0113E_cortex_m3_r2p0_im/DII0113.book
docs/DII0113E_cortex_m3_r2p0_im/DII0113LOF.fm
docs/DII0113E_cortex_m3_r2p0_im/DII0113LOT.fm
docs/DII0113E_cortex_m3_r2p0_im/DII0113TOC.fm
docs/DII0113E_cortex_m3_r2p0_im/graphics/
docs/DII0113E_cortex_m3_r2p0_im/graphics/clock_latency.svg
docs/DII0113E_cortex_m3_r2p0_im/graphics/clock_latency.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/correct_signal_connections.svg
docs/DII0113E_cortex_m3_r2p0_im/graphics/correct_signal_connections.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/cortexm3Integration_level_interfaces.svg
docs/DII0113E_cortex_m3_r2p0_im/graphics/cortexm3Integration_level_interfaces.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/cortexm3_level_interfaces.svg
docs/DII0113E_cortex_m3_r2p0_im/graphics/cortexm3_level_interfaces.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/dynamic_verification_process.svg
docs/DII0113E_cortex_m3_r2p0_im/graphics/dynamic_verification_process.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/example_system_directory_structure.svg
docs/DII0113E_cortex_m3_r2p0_im/graphics/example_system_directory_structure.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/extest_mode_of_operation.svg
docs/DII0113E_cortex_m3_r2p0_im/graphics/extest_mode_of_operation.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/integration_design_flow.svg
docs/DII0113E_cortex_m3_r2p0_im/graphics/integration_design_flow.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/intest_mode_of_operation.svg
docs/DII0113E_cortex_m3_r2p0_im/graphics/intest_mode_of_operation.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/key_to_timing_diagram_conventions.eps
docs/DII0113E_cortex_m3_r2p0_im/graphics/key_to_timing_diagram_conventions.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/lec_verification_process.eps
docs/DII0113E_cortex_m3_r2p0_im/graphics/lec_verification_process.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/macrocell_block_view.svg
docs/DII0113E_cortex_m3_r2p0_im/graphics/macrocell_block_view.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/physical_integration_process.svg
docs/DII0113E_cortex_m3_r2p0_im/graphics/physical_integration_process.vsd
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docs/DII0113E_cortex_m3_r2p0_im/graphics/preprocessing_scripts_flow.svg
docs/DII0113E_cortex_m3_r2p0_im/graphics/preprocessing_scripts_flow.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/reset_signals.svg
docs/DII0113E_cortex_m3_r2p0_im/graphics/reset_signals.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/shadow_logic.svg
docs/DII0113E_cortex_m3_r2p0_im/graphics/shadow_logic.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/soc_integration_examples.svg
docs/DII0113E_cortex_m3_r2p0_im/graphics/soc_integration_examples.vsd
docs/DII0113E_cortex_m3_r2p0_im/graphics/sta_verification_process.eps
docs/DII0113E_cortex_m3_r2p0_im/graphics/sta_verification_process.vsd
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docs/DII0113E_cortex_m3_r2p0_im/graphics/synthesis_process.vsd
docs/DII0113E_cortex_m3_r2p0_im/IM_bookinfo.fm
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docs/DII0113E_cortex_m3_r2p0_im/IM_dft_guidelines.fm
docs/DII0113E_cortex_m3_r2p0_im/IM_dft_verification.fm
docs/DII0113E_cortex_m3_r2p0_im/IM_example_system.fm
docs/DII0113E_cortex_m3_r2p0_im/IM_functional_integration_guidelines.fm
docs/DII0113E_cortex_m3_r2p0_im/IM_glossary.fm
docs/DII0113E_cortex_m3_r2p0_im/IM_introduction.fm
docs/DII0113E_cortex_m3_r2p0_im/IM_key_integration_points.fm
docs/DII0113E_cortex_m3_r2p0_im/IM_physical_integration_guidelines.fm
docs/DII0113E_cortex_m3_r2p0_im/IM_post_layout_verification.fm
docs/DII0113E_cortex_m3_r2p0_im/IM_preface.fm
docs/DII0113E_cortex_m3_r2p0_im/IM_revisions.fm
docs/DII0113E_cortex_m3_r2p0_im/IM_sign_off.fm
docs/DII0113E_cortex_m3_r2p0_im/readme.txt

AT420-MN-25001-r2p0-00rel0:

example/
example/tbench/
example/tbench/example_tbench.vc
example/tbench/CM3ExampleConfig.vh
example/tbench/example_tbench.v
example/tbench/DefaultSlave.v
example/tbench/ApbLogger.v
example/tbench/CM3_ApbLogger.v
example/tbench/TrickBox.v
example/tbench/SinglePortRAM.v
example/tbench/etmvaltracelogger.v
example/tbench/CM3_AtbLogger.v
example/tbench/DualPortROM.v
example/tbench/TPIUMonitor.v
example/tbench/DualPortRAM.v
example/tbench/TBenchDebug.v
example/tbench/ecslogger.v
example/run_example
example/coresight/
example/coresight/tests/
example/coresight/tests/src/
example/coresight/tests/Makefile.common
example/coresight/tests/bin/
example/coresight/tests/Makefile
example/coresight/doc/
example/coresight/doc/DAPMacroLanguage.pdf
example/coresight/doc/BSTUserGuide.pdf
example/coresight/doc/SWJIMUserGuide.pdf
example/coresight/shared/
example/coresight/shared/logical/
example/coresight/shared/logical/bin/
example/coresight/shared/logical/bin/SWJIMCtlconvert.pl
example/coresight/shared/logical/bin/SWIMconvert.pl
example/coresight/shared/logical/bin/DAPbsi.pl
example/coresight/logical/
example/coresight/logical/armBST/
example/coresight/logical/armBST/HPUX/
example/coresight/logical/armBST/HPUX/armBST.sl
example/coresight/logical/armBST/HPUX/pli.tab
example/coresight/logical/armBST/HPUX/armBST.v
example/coresight/logical/armBST/SunOS5_64/
example/coresight/logical/armBST/SunOS5_64/armBST.so
example/coresight/logical/armBST/SunOS5_64/pli.tab
example/coresight/logical/armBST/SunOS5_64/armBST.v
example/coresight/logical/armBST/RH_Linux_x86_64/
example/coresight/logical/armBST/RH_Linux_x86_64/armBST.so
example/coresight/logical/armBST/RH_Linux_x86_64/pli.tab
example/coresight/logical/armBST/RH_Linux_x86_64/armBST.v
example/coresight/logical/armBST/ModelManager/
example/coresight/logical/armBST/ModelManager/Linux/
example/coresight/logical/armBST/ModelManager/Linux/MM/
example/coresight/logical/armBST/ModelManager/Linux/MM/cadence_nc_verilog/
example/coresight/logical/armBST/ModelManager/Linux/MM/cadence_nc_verilog/libmgmm.so
example/coresight/logical/armBST/ModelManager/Linux/MM/cadence_nc_verilog/MM_cadence_nc_verilog.txt
example/coresight/logical/armBST/ModelManager/Linux/MM/cadence_nc_verilog/mm_nc_dynamic.so
example/coresight/logical/armBST/ModelManager/Linux/MM/mti_modelsim_verilog/
example/coresight/logical/armBST/ModelManager/Linux/MM/mti_modelsim_verilog/libmgmm.so
example/coresight/logical/armBST/ModelManager/Linux/MM/mti_modelsim_verilog/MM_mti_modelsim_verilog.txt
example/coresight/logical/armBST/ModelManager/Linux/MM/synopsys_vcs_verilog/
example/coresight/logical/armBST/ModelManager/Linux/MM/synopsys_vcs_verilog/libmgmm.so
example/coresight/logical/armBST/ModelManager/Linux/MM/synopsys_vcs_verilog/MM_synopsys_vcs_verilog.txt
example/coresight/logical/armBST/ModelManager/SunOS_64/
example/coresight/logical/armBST/ModelManager/SunOS_64/MM/
example/coresight/logical/armBST/ModelManager/SunOS_64/MM/cadence_nc_verilog/
example/coresight/logical/armBST/ModelManager/SunOS_64/MM/cadence_nc_verilog/libmgmm.so
example/coresight/logical/armBST/ModelManager/SunOS_64/MM/cadence_nc_verilog/MM_cadence_nc_verilog.txt
example/coresight/logical/armBST/ModelManager/SunOS_64/MM/cadence_nc_verilog/mm_nc_dynamic.so
example/coresight/logical/armBST/ModelManager/SunOS_64/MM/mti_modelsim_verilog/
example/coresight/logical/armBST/ModelManager/SunOS_64/MM/mti_modelsim_verilog/libmgmm.so
example/coresight/logical/armBST/ModelManager/SunOS_64/MM/mti_modelsim_verilog/MM_mti_modelsim_verilog.txt
example/coresight/logical/armBST/ModelManager/SunOS_64/MM/synopsys_vcs_verilog/
example/coresight/logical/armBST/ModelManager/SunOS_64/MM/synopsys_vcs_verilog/libmgmm.so
example/coresight/logical/armBST/ModelManager/SunOS_64/MM/synopsys_vcs_verilog/MM_synopsys_vcs_verilog.txt
example/coresight/logical/armBST/ModelManager/HP-UX/
example/coresight/logical/armBST/ModelManager/HP-UX/MM/
example/coresight/logical/armBST/ModelManager/HP-UX/MM/cadence_nc_verilog/
example/coresight/logical/armBST/ModelManager/HP-UX/MM/cadence_nc_verilog/libmgmm.sl
example/coresight/logical/armBST/ModelManager/HP-UX/MM/cadence_nc_verilog/MM_cadence_nc_verilog.txt
example/coresight/logical/armBST/ModelManager/HP-UX/MM/cadence_nc_verilog/mm_nc_dynamic.sl
example/coresight/logical/armBST/ModelManager/HP-UX/MM/mti_modelsim_verilog/
example/coresight/logical/armBST/ModelManager/HP-UX/MM/mti_modelsim_verilog/libmgmm.so
example/coresight/logical/armBST/ModelManager/HP-UX/MM/mti_modelsim_verilog/MM_mti_modelsim_verilog.txt
example/coresight/logical/armBST/ModelManager/HP-UX/MM/synopsys_vcs_verilog/
example/coresight/logical/armBST/ModelManager/HP-UX/MM/synopsys_vcs_verilog/libmgmm.sl
example/coresight/logical/armBST/ModelManager/HP-UX/MM/synopsys_vcs_verilog/MM_synopsys_vcs_verilog.txt
example/coresight/logical/armBST/ModelManager/SunOS/
example/coresight/logical/armBST/ModelManager/SunOS/MM/
example/coresight/logical/armBST/ModelManager/SunOS/MM/cadence_nc_verilog/
example/coresight/logical/armBST/ModelManager/SunOS/MM/cadence_nc_verilog/libmgmm.so
example/coresight/logical/armBST/ModelManager/SunOS/MM/cadence_nc_verilog/MM_cadence_nc_verilog.txt
example/coresight/logical/armBST/ModelManager/SunOS/MM/cadence_nc_verilog/mm_nc_dynamic.so
example/coresight/logical/armBST/ModelManager/SunOS/MM/mti_modelsim_verilog/
example/coresight/logical/armBST/ModelManager/SunOS/MM/mti_modelsim_verilog/libmgmm.so
example/coresight/logical/armBST/ModelManager/SunOS/MM/mti_modelsim_verilog/MM_mti_modelsim_verilog.txt
example/coresight/logical/armBST/ModelManager/SunOS/MM/synopsys_vcs_verilog/
example/coresight/logical/armBST/ModelManager/SunOS/MM/synopsys_vcs_verilog/libmgmm.so
example/coresight/logical/armBST/ModelManager/SunOS/MM/synopsys_vcs_verilog/MM_synopsys_vcs_verilog.txt
example/coresight/logical/armBST/ModelManager/Linux_64/
example/coresight/logical/armBST/ModelManager/Linux_64/MM/
example/coresight/logical/armBST/ModelManager/Linux_64/MM/cadence_nc_verilog/
example/coresight/logical/armBST/ModelManager/Linux_64/MM/cadence_nc_verilog/libmgmm.so
example/coresight/logical/armBST/ModelManager/Linux_64/MM/cadence_nc_verilog/MM_cadence_nc_verilog.txt
example/coresight/logical/armBST/ModelManager/Linux_64/MM/cadence_nc_verilog/mm_nc_dynamic.so
example/coresight/logical/armBST/ModelManager/Linux_64/MM/mti_modelsim_verilog/
example/coresight/logical/armBST/ModelManager/Linux_64/MM/mti_modelsim_verilog/libmgmm.so
example/coresight/logical/armBST/ModelManager/Linux_64/MM/mti_modelsim_verilog/MM_mti_modelsim_verilog.txt
example/coresight/logical/armBST/ModelManager/Linux_64/MM/synopsys_vcs_verilog/
example/coresight/logical/armBST/ModelManager/Linux_64/MM/synopsys_vcs_verilog/libmgmm.so
example/coresight/logical/armBST/ModelManager/Linux_64/MM/synopsys_vcs_verilog/MM_synopsys_vcs_verilog.txt
example/coresight/logical/armBST/SunOS5/
example/coresight/logical/armBST/SunOS5/armBST.so
example/coresight/logical/armBST/SunOS5/pli.tab
example/coresight/logical/armBST/SunOS5/armBST.v
example/coresight/logical/armBST/RH_Linux_x86/
example/coresight/logical/armBST/RH_Linux_x86/armBST.so
example/coresight/logical/armBST/RH_Linux_x86/pli.tab
example/coresight/logical/armBST/RH_Linux_x86/armBST.v
example/coresight/logical/SWJIM/
example/coresight/logical/SWJIM/SWJIMCtl.v
example/coresight/logical/SWJIM/SWIM.v
example/coresight/logical/SWJIM/BSTMon.v
example/coresight/logical/SWJIM/SWJIMMux.v
example/coresight/logical/SWJIM/SWDriver.v
example/coresight/logical/SWJIM/WIDefines.vh
example/coresight/logical/SWJIM/WiProtocolEngine.v
example/coresight/logical/SWJIM/WireControl.v
example/coresight/logical/SWJIM/WireInterface.v
example/coresight/logical/SWJIM/SWJIM.v
example/bin/
example/bin/Etm/
example/bin/Etm/PerfMon.pm
example/bin/Etm/Decomp.pm
example/bin/Etm/TraceV3.pm
example/bin/Etm/ECS.pm
example/bin/Etm/Resources.pm
example/bin/Etm/CompItem.pm
example/bin/Etm/CycleTube.pm
example/bin/Etm/APBParser.pm
example/bin/Etm/DecompV3.pm
example/bin/Etm/ToolsOutput.pm
example/bin/Etm/CovBase.pm
example/bin/Etm/Programming.pm
example/bin/Etm/JTAG.pm
example/bin/Etm/SyncV3.pm
example/bin/Etm/Disass.pm
example/bin/Etm/Compare.pm
example/bin/Etm/TraceV3_1.pm
example/bin/Etm/Coverage.pm
example/bin/Etm/CompArray.pm
example/bin/Etm/Trace.pm
example/bin/Etm/Output.pm
example/bin/Etm/RomImage.pm
example/bin/Etm/ProcArch.pm
example/bin/Etm/ProgVerif.pm
example/bin/bin2hex
example/bin/EtbCompare
example/bin/bintobst
example/bin/decode_ITM_stream.pl
example/bin/parse_bsi.pl
example/bin/modules/
example/bin/modules/HTMMisc.pm
example/bin/modules/ETBExtract.pm
example/bin/modules/Unformatter.pm
example/bin/modules/AHBParser.pm
example/bin/modules/TPIUExtract.pm
example/bin/modules/HTMDecompressor.pm
example/bin/modules/APBParser.pm
example/bin/modules/ETMTracePortCompare.pm
example/bin/modules/ETBCompare.pm
example/bin/modules/HTMResources.pm
example/bin/modules/ATBParser.pm
example/bin/modules/TPIUProgramming.pm
example/bin/modules/InstrTraceCompare.pm
example/bin/modules/TPIUCompare.pm
example/bin/modules/FunnelCompare.pm
example/bin/modules/TPIUParser.pm
example/bin/modules/HTMCompare.pm
example/bin/modules/Output.pm
example/bin/modules/Formatter.pm
example/bin/hextohbin
example/bin/CSCompare
example/bin/EtmCompare
example/bin/diff-format.txt
example/Software/
example/Software/cm3_codeANDdata_on_codebus.scat
example/Software/CM3_J_CM3Trace1.cdapml
example/Software/test_dhry.c
example/Software/test_mla.c
example/Software/cortexm3.h
example/Software/clib.c
example/Software/dhry.h
example/Software/cm3_code_on_codebus.scat
example/Software/clib_min.c
example/Software/README
example/Software/serial.c
example/Software/exceptions.c
example/Software/test_apb1.c
example/Software/stackheap.s
example/Software/CM3_S_CM3Trace1.cdapml
example/Software/cm3_code_on_codebus_min.scat
example/Software/exceptions_min.c
example/Software/dhry_1.c
example/Software/dhry_2.c
example/Software/cm3_code_on_sysbus.scat
example/Software/dummy.ramhex
example/Software/my_dhry_1.c
example/Software/Makefile
example/Software/Crack_cdapml.pl
example/Software/my_dhry_2.c
example/EtmCompare.cfg
example/README

AT420-VE-09001-r2p0-00rel0:

implementation/
implementation/CortexM3/
implementation/CortexM3/vectors/
implementation/CortexM3/vectors/src/
implementation/CortexM3/vectors/src/Portable_TypPower.s

AT420-VE-70006-r2p0-00rel0:

implementation/
implementation/CortexM3/
implementation/CortexM3/vectors/
implementation/CortexM3/vectors/src/
implementation/CortexM3/vectors/src/Portable_Instruction.s

AT420-VE-70007-r2p0-00rel0:

implementation/
implementation/CortexM3/
implementation/CortexM3/vectors/
implementation/CortexM3/vectors/src/
implementation/CortexM3/vectors/src/Portable_MaxSpeed.s

AT420-VE-70025-r2p0-00rel0:

implementation/
implementation/CortexM3/
implementation/CortexM3/vectors/
implementation/CortexM3/vectors/src/
implementation/CortexM3/vectors/src/Portable_MaxPower.s

AT425-DC-06001-r2p0-00rel0:

Cortex-M3+ETM_Release_Note.pdf

AT425-MN-22100-r2p0-00rel0:

logical/
logical/CM3BusMatrix/
logical/CM3BusMatrix/verilog/
logical/CM3BusMatrix/verilog/CM3BMBitMaster.v
logical/CM3BusMatrix/verilog/CM3BMDecode3dap.v
logical/CM3BusMatrix/verilog/CM3BusMatrix.v
logical/CM3BusMatrix/verilog/CM3BMOutputStage1.v
logical/CM3BusMatrix/verilog/CM3BMDecode2.v
logical/CM3BusMatrix/verilog/CM3BMOutputStage2.v
logical/CM3BusMatrix/verilog/CM3BMOutputArb1.v
logical/CM3BusMatrix/verilog/CM3BMDecode3.v
logical/CM3BusMatrix/verilog/CM3BMOutputArb2.v
logical/CM3BusMatrix/verilog/CM3BMInputStageDap.v
logical/CM3BusMatrix/verilog/CM3BMInputStageWB.v
logical/CM3BusMatrix/verilog/CM3BMDefs.v
logical/CM3BusMatrix/verilog/CM3BMInputStage.v
logical/CM3BusMatrix/verilog/CM3BMOutputStage2BM.v
logical/CM3BusMatrix/verilog/CM3BMOutputStage3BM.v
logical/CM3BusMatrix/verilog/CM3BMOutputArb2BM.v
logical/CM3BusMatrix/verilog/CM3BMOutputArb3BM.v
logical/models/
logical/models/cells/
logical/models/cells/CM3EtmClkGate.v
logical/models/cells/CM3ClkGate.v
logical/models/cells/CM3Sync.v
logical/CM3CoreSys/
logical/CM3CoreSys/verilog/
logical/CM3CoreSys/verilog/CM3NVICPPBIntf.v
logical/CM3CoreSys/verilog/CM3CoreLSUWPort.v
logical/CM3CoreSys/verilog/CM3CoreLSUAHBIntf.v
logical/CM3CoreSys/verilog/CM3CoreLSU.v
logical/CM3CoreSys/verilog/CM3CoreDP.v
logical/CM3CoreSys/verilog/CM3CoreLSUState.v
logical/CM3CoreSys/verilog/CM3CoreETMIntf.v
logical/CM3CoreSys/verilog/CM3NVICTree.v
logical/CM3CoreSys/verilog/CM3CoreALUMove.v
logical/CM3CoreSys/verilog/CM3NVICPreempt.v
logical/CM3CoreSys/verilog/CM3CoreSys.v
logical/CM3CoreSys/verilog/CM3CoreALU.v
logical/CM3CoreSys/verilog/CM3CoreALUBShift.v
logical/CM3CoreSys/verilog/CM3CoreALUMult.v
logical/CM3CoreSys/verilog/CM3CoreFetchWPort.v
logical/CM3CoreSys/verilog/CM3CoreFetchAHBIntf.v
logical/CM3CoreSys/verilog/CM3NVIC.v
logical/CM3CoreSys/verilog/CM3NVICDefs.v
logical/CM3CoreSys/verilog/CM3CoreRegFile2R1W.v
logical/CM3CoreSys/verilog/CM3CoreFetch.v
logical/CM3CoreSys/verilog/CM3CoreFetchState.v
logical/CM3CoreSys/verilog/CM3CoreDec.v
logical/CM3CoreSys/verilog/CM3NVICMain.v
logical/CM3CoreSys/verilog/CM3CoreALURBit.v
logical/CM3CoreSys/verilog/CM3NVICIntState.v
logical/CM3CoreSys/verilog/CM3CoreALUDP.v
logical/CM3CoreSys/verilog/CM3CoreLSUCtl.v
logical/CM3CoreSys/verilog/CM3CoreRegBank.v
logical/CM3CoreSys/verilog/CM3CoreALUSRTDiv.v
logical/CM3CoreSys/verilog/CM3Core.v
logical/CM3CoreSys/verilog/CM3CoreDefs.v
logical/CM3CoreSys/verilog/CM3CoreALUCtl.v
logical/CM3CoreSys/verilog/CM3CoreExec.v
logical/CM3CoreSys/verilog/CM3NVICReg.v
logical/CM3CoreSys/verilog/CM3NVICCell.v
logical/CM3CoreSys/verilog/CM3CoreLSURPort.v
logical/CM3CoreSys/verilog/CM3CoreALUCLZ.v
logical/CM3CoreSys/verilog/CM3CoreFlags.v
logical/CM3ITM/
logical/CM3ITM/verilog/
logical/CM3ITM/verilog/CM3ITMEmit.v
logical/CM3ITM/verilog/CM3ITMIf.v
logical/CM3ITM/verilog/CM3ITM.v
logical/CM3ITM/verilog/CM3ITMFifo.v
logical/CM3ITM/verilog/CM3ITMArb.v
logical/CM3ITM/verilog/CM3ITMCtrl.v
logical/CM3ITM/verilog/CM3ITMTS.v
logical/CM3ITM/verilog/CM3ITMFifoByte.v
logical/CM3DWT/
logical/CM3DWT/verilog/
logical/CM3DWT/verilog/CM3DWTComp.v
logical/CM3DWT/verilog/CM3DWT.v
logical/CM3DWT/verilog/CM3DWTDefs.v
logical/CM3DWT/verilog/CM3DWTPacketGen.v
logical/CM3DWT/verilog/CM3DWTEmitCtrl.v
logical/tbench/
logical/CortexM3/
logical/CortexM3/verilog/
logical/CortexM3/verilog/CM3HTMPort.v
logical/CortexM3/verilog/CM3PPBAHB2APB.v
logical/CortexM3/verilog/CortexM3.v
logical/CortexM3/verilog/CM3PPBDecoder.v
logical/CM3MPU/
logical/CM3MPU/verilog/
logical/CM3MPU/verilog/CM3MPURegions.v
logical/CM3MPU/verilog/CM3MPUAlign.v
logical/CM3MPU/verilog/CM3MPUAHBCtl.v
logical/CM3MPU/verilog/CM3MPUComp.v
logical/CM3MPU/verilog/CM3MPU.v
logical/CM3MPU/verilog/CM3MPUDefs.v
logical/CM3MPU/verilog/CM3MPUFull.v
logical/CM3MPU/verilog/CM3MPUPPBIntf.v
logical/CM3MPU/verilog/CM3MPURegion.v
logical/CM3MPU/verilog/CM3MPUDefault.v
logical/CM3MPU/verilog/CM3MPUMaskGen.v
logical/CM3DAP/
logical/CM3DAP/verilog/
logical/CM3DAP/verilog/CM3DAPAhbApSync.v
logical/CM3DAP/verilog/CM3DAPAHBAP.v
logical/CM3DAP/verilog/CM3DAPAhbApAbtSync.v
logical/CM3DAP/verilog/CM3DAPAhbApMst.v
logical/CM3DAP/verilog/CM3DAPAhbApSlv.v
logical/CM3FPB/
logical/CM3FPB/verilog/
logical/CM3FPB/verilog/CM3FPB.v
logical/dapswjdp/
logical/dapswjdp/verilog/
logical/dapswjdp/README_DAPSWJDP

AT425-MN-22101-r2p0-00rel0:

logical/
logical/tbench/
logical/tbench/verilog/
logical/tbench/verilog/CM3ValTraceUnpack.v
logical/tbench/verilog/tarmacE.v
logical/tbench/verilog/ClkReset.v
logical/tbench/verilog/CM3ValTBDefs.v
logical/tbench/verilog/CM3ValApbTrickBox.v
logical/tbench/verilog/tarmacI.v
logical/tbench/verilog/AhbToApb.v
logical/tbench/verilog/CM3ValScratchPad.v
logical/tbench/verilog/tarmacM.v
logical/tbench/verilog/TBenchApbLogger.v
logical/tbench/verilog/WiProtocolEngine.v
logical/tbench/verilog/CM3ValIRQGenerator1.v
logical/tbench/verilog/CM3ValBusCompareCtrlReg.v
logical/tbench/verilog/CM3ValDualPortRAM.v
logical/tbench/verilog/CM3ValETMTrickBox.v
logical/tbench/verilog/CM3ValJtagTrickBox.v
logical/tbench/verilog/tbench.v
logical/tbench/verilog/CM3ValHTMTrickBox.v
logical/tbench/verilog/AtbLogger.v
logical/tbench/verilog/ecslogger_dsm.v
logical/tbench/verilog/etmvaltracelogger.v
logical/tbench/verilog/WireControl.v
logical/tbench/verilog/CM3ValTraceSync.v
logical/tbench/verilog/BusMatrix.v
logical/tbench/verilog/CM3ValMemory.v
logical/tbench/verilog/DualAhbTube.v
logical/tbench/verilog/CM3ValSWCapture.v
logical/tbench/verilog/CM3BusComparator.v
logical/tbench/verilog/CM3ValRAM.v
logical/tbench/verilog/CM3ValRAMWrapper.v
logical/tbench/verilog/DapClkGen.v
logical/tbench/verilog/CM3ValTrickBox.v
logical/tbench/verilog/CM3ValPMU.v
logical/tbench/verilog/dt2_32.vh
logical/tbench/verilog/CM3ValDebugCore.v
logical/tbench/verilog/dt2_16.vh
logical/tbench/verilog/tbench_dsm.vc
logical/tbench/verilog/MatrixDecode.v
logical/tbench/verilog/ecslogger.v
logical/tbench/verilog/tarmacB.v
logical/tbench/verilog/CM3ValTraceOutput.v
logical/tbench/verilog/tarmacDSM.v
logical/tbench/verilog/CM3ValAHBSplit.v
logical/tbench/verilog/WIDefines.v
logical/tbench/verilog/TraceClkGen.v
logical/tbench/verilog/etmvaltracelogger_dsm.v
logical/tbench/verilog/LogDefs_dsm.v
logical/tbench/verilog/CM3ValControl.v
logical/tbench/verilog/WireInterface.v
logical/tbench/verilog/tarmacR.v
logical/tbench/verilog/CM3ValIRQGenerator2.v
logical/tbench/verilog/DapBusSwitch.v
logical/tbench/verilog/CM3ValDualPortWrapper.v
logical/tbench/verilog/dt2_common.vh
logical/tbench/verilog/tarmac.vh
logical/tbench/verilog/InputStage.v
logical/tbench/verilog/OutputStage.v
logical/tbench/verilog/OutputArb.v
logical/tbench/verilog/CM3TestExAcMnAhb.v
logical/tbench/verilog/CM3BusGasket.v
logical/tbench/verilog/dt2_arm.vh
logical/tbench/verilog/tbench.vc
logical/tbench/verilog/tarmac.v
logical/tbench/verilog/dt2_disass.vh

AT425-MN-70005-r2p0-00rel0:

logical/
logical/dapswjdp/
logical/dapswjdp/verilog/
logical/dapswjdp/verilog/DAPDpApbDefs.v
logical/dapswjdp/verilog/DAPDpApbIfClamp.v
logical/dapswjdp/verilog/DAPDpApbSync.v
logical/dapswjdp/verilog/DAPDpClamp0.v
logical/dapswjdp/verilog/DAPDpEnSync.v
logical/dapswjdp/verilog/DAPDpIMux.v
logical/dapswjdp/verilog/DAPDpSync.v
logical/dapswjdp/verilog/DAPJtagDpDefs.v
logical/dapswjdp/verilog/DAPJtagDpProtocol.v
logical/dapswjdp/verilog/DAPSWJDP.v
logical/dapswjdp/verilog/DAPSwDpApbIf.v
logical/dapswjdp/verilog/DAPSwDpDefs.v
logical/dapswjdp/verilog/DAPSwDpProtocol.v
logical/dapswjdp/verilog/DAPSwDpSync.v
logical/dapswjdp/verilog/DAPSwjDpDefs.v
logical/dapswjdp/verilog/DAPSwjWatcher.v
logical/CortexM3Integration/
logical/CortexM3Integration/verilog/
logical/CortexM3Integration/verilog/CM3CodeMux.v
logical/CortexM3Integration/verilog/CM3ROMTable.v
logical/CortexM3Integration/verilog/CortexM3Integration.v
logical/CortexM3Integration/verilog/CM3flashmux.v
logical/CM3TPIU/
logical/CM3TPIU/verilog/
logical/CM3TPIU/verilog/CM3TPIUTraceOut.v
logical/CM3TPIU/verilog/CM3TPIUTraceClk.v
logical/CM3TPIU/verilog/CM3TPIUAtbFifo.v
logical/CM3TPIU/verilog/CM3TPIUTraceSync.v
logical/CM3TPIU/verilog/CM3TPIUSync.v
logical/CM3TPIU/verilog/CM3TPIU.v
logical/CM3TPIU/verilog/CM3TPIUApbIf.v
logical/CM3TPIU/verilog/CM3TPIUDefs.v
logical/CM3TPIU/verilog/CM3TPIUTraceFifo.v
logical/CM3TPIU/verilog/CM3TPIUAtbSync.v
logical/CM3TPIU/verilog/CM3TPIUFormatter.v
logical/CM3ETM/
logical/CM3ETM/verilog/
logical/CM3ETM/verilog/CM3EtmSyncCount.v
logical/CM3ETM/verilog/CM3EtmTrigger.v
logical/CM3ETM/verilog/CM3EtmEventGenMux.v
logical/CM3ETM/verilog/CM3EtmGen.v
logical/CM3ETM/verilog/CM3EtmTrcEn.v
logical/CM3ETM/verilog/CM3EtmMiniRotate.v
logical/CM3ETM/verilog/CM3EtmEventGen.v
logical/CM3ETM/verilog/CM3EtmControlReg.v
logical/CM3ETM/verilog/CM3ETM.v
logical/CM3ETM/verilog/CM3EtmDefs.v
logical/CM3ETM/verilog/CM3EtmAPBif.v
logical/CM3ETM/verilog/CM3EtmFifo.v
logical/CM3ETM/verilog/CM3EtmTraceOut.v
logical/CM3ETM/verilog/CM3EtmAddrComp.v
logical/CM3ETM/verilog/CM3EtmResControl.v
logical/CM3ETM/verilog/CM3EtmTrace.v
logical/CM3ETM/verilog/CM3EtmTrigGen.v
logical/CM3WIC/
logical/CM3WIC/verilog/
logical/CM3WIC/verilog/CM3ExamplePMU.v
logical/CM3WIC/verilog/CM3WIC.v

AT425-VA-04001-r2p0-00rel0:

README_validation
validation/
validation/glogs.tar.gz
validation/validation.cfg
validation/tn_isa/
validation/tn_isa/exclude_list.sc_systick
validation/tn_isa/src/
validation/tn_isa/src/source_list
validation/tn_isa/exclude_list.sc_waitstate
validation/tn_isa/exclude_list.sc_hwstep
validation/tn_isa/exclude_list.sc_monstep
validation/tn_mpu/
validation/tn_mpu/exclude_list.sc_systick
validation/tn_mpu/src/
validation/tn_mpu/src/source_list
validation/tn_mpu/exclude_list.sc_hwstep
validation/tn_mpu/exclude_list.sc_monstep
validation/cm3_nvic/
validation/cm3_nvic/exclude_list.etmEnTrcSW
validation/cm3_nvic/exclude_list.etmRandTrcSW
validation/cm3_nvic/exclude_list.sc_systick
validation/cm3_nvic/src/
validation/cm3_nvic/src/source_list
validation/cm3_nvic/exclude_list.sc_waitstate
validation/cm3_nvic/exclude_list.sc_hwstep
validation/cm3_nvic/exclude_list.sc_monstep
validation/val_report.cfg
validation/reports/
validation/reports/cortex-m3.rep
validation/generic/
validation/generic/include/
validation/generic/include/src/
validation/generic/include/src/script.ld
validation/generic/tools/
validation/generic/tools/solaris/
validation/generic/tools/solaris/elf2hex
validation/generic/tools/solaris/bin2elf
validation/generic/tools/linux/
validation/generic/tools/linux/elf2hex
validation/generic/tools/linux/bin2elf
validation/generic/tools/hpux/
validation/generic/tools/bin/
validation/generic/tools/bin/vf_percent_csv
validation/generic/tools/bin/array_runner
validation/generic/tools/bin/gather_elfs
validation/generic/tools/bin/bin2hex
validation/generic/tools/bin/val_report.bat
validation/generic/tools/bin/val_job_runner
validation/generic/tools/bin/elf2bin
validation/generic/tools/bin/bintobst
validation/generic/tools/bin/vf_percent
validation/generic/tools/bin/vf_percent_html
validation/generic/tools/bin/val_report
validation/generic/tools/bin/parse_bsi.pl
validation/generic/tools/bin/validation
validation/gbins.tar.gz
validation/etmv3_4/
validation/etmv3_4/exclude_list.etmEnTrcSW
validation/etmv3_4/exclude_list.ETM
validation/etmv3_4/src/
validation/etmv3_4/src/source_list
validation/etmv3_4/exclude_list.noetmTrc
validation/cm3_errata/
validation/cm3_errata/src/
validation/cm3_errata/src/source_list
validation/tn_arch/
validation/tn_arch/exclude_list.etmEnTrcSW
validation/tn_arch/exclude_list.etmRandTrcSW
validation/tn_arch/exclude_list.sc_systick
validation/tn_arch/src/
validation/tn_arch/src/source_list
validation/tn_arch/exclude_list.sc_waitstate
validation/tn_arch/exclude_list.sc_hwstep
validation/tn_arch/exclude_list.sc_monstep
validation/etmm3/
validation/etmm3/exclude_list.etmEnTrcSW
validation/etmm3/exclude_list.ETMnocmp
validation/etmm3/exclude_list.ETM
validation/etmm3/src/
validation/etmm3/src/source_list
validation/etmm3/exclude_list.etmEnTrcSWnocmp
validation/etmm3/exclude_list.noetmTrc
validation/etmm3/exclude_list.etmEnTrcSW_tpiu1
validation/etmm3/configs/
validation/etmm3/configs/etmRandTrcSW.cfg
validation/etmm3/configs/noetmTrc.cfg
validation/etmm3/configs/etmEnTrcSWnocmp.cfg
validation/etmm3/configs/etmRandRsrc.cfg
validation/etmm3/configs/etmBB.cfg
validation/etmm3/configs/etmNoBB.cfg
validation/etmm3/configs/etmEnTrcSW_tpiu1.cfg
validation/etmm3/configs/ecscompare.cfg
validation/etmm3/configs/etmm3.cfg
validation/etmm3/configs/ETM.cfg
validation/etmm3/configs/etmEnTrcSW.cfg
validation/etmm3/configs/tpiu1.cfg
validation/dotcshrc
validation/cm3_dbg/
validation/cm3_dbg/exclude_list.etmEnTrcSW
validation/cm3_dbg/exclude_list.sc_systick
validation/cm3_dbg/exclude_list.ETM
validation/cm3_dbg/src/
validation/cm3_dbg/src/source_list
validation/cm3_dbg/exclude_list.etmRandRsrc
validation/cm3_dbg/exclude_list.sc_waitstate
validation/cortex-m3.list
validation/cm3_wic/
validation/cm3_wic/src/
validation/cm3_wic/src/source_list
validation/cm3_wic/exclude_list.sc_waitstate
validation/sandcat/
validation/sandcat/src/
validation/sandcat/src/source_list
validation/sandcat/configs/
validation/sandcat/configs/sc_hwstep.cfg
validation/sandcat/configs/sc_systick.cfg
validation/sandcat/configs/sc_monstep.cfg
validation/sandcat/configs/dummy.cfg
validation/sandcat/configs/sc_waitstate.cfg
validation/cm3_mem/
validation/cm3_mem/exclude_list.etmEnTrcSW
validation/cm3_mem/exclude_list.etmRandTrcSW
validation/cm3_mem/exclude_list.sc_systick
validation/cm3_mem/src/
validation/cm3_mem/src/source_list
validation/cm3_mem/exclude_list.sc_hwstep
validation/cm3_mem/exclude_list.sc_monstep
validation/tn_debug/
validation/tn_debug/exclude_list.etmEnTrcSW
validation/tn_debug/exclude_list.etmRandTrcSW
validation/tn_debug/exclude_list.sc_systick
validation/tn_debug/src/
validation/tn_debug/src/source_list
validation/tn_debug/exclude_list.sc_waitstate

AT425-VE-70000-r2p0-00rel0:

implementation/
implementation/CortexM3/
implementation/CortexM3/vectors/
implementation/CortexM3/vectors/crf/
implementation/CortexM3/vectors/crf/CortexM3.ctrm
implementation/CortexM3/vectors/crf/CortexM3.Portable_Instruction.capture.log.Z
implementation/CortexM3/vectors/crf/CortexM3.Portable_Instruction.crf.Z
implementation/CortexM3/vectors/crf/CortexM3.Portable_Instruction_netlist.replay.log.Z
implementation/CortexM3/vectors/crf/CortexM3.Portable_Instruction_verilog.replay.log.Z
implementation/CortexM3/vectors/tbench/
implementation/CortexM3/vectors/tbench/VerilogCrf/
implementation/CortexM3/vectors/tbench/VerilogCrf/Ctrm.pm
implementation/CortexM3/vectors/tbench/BuildVerilogMTI
implementation/CortexM3/vectors/tbench/BuildNetlistNC
implementation/CortexM3/vectors/tbench/BuildVerilogVCS
implementation/CortexM3/vectors/tbench/ReplayMTI
implementation/CortexM3/vectors/tbench/BuildVerilogNC
implementation/CortexM3/vectors/tbench/ReplayVCS
implementation/CortexM3/vectors/tbench/CortexM3_Replay_tb.v
implementation/CortexM3/vectors/tbench/netlist.vc
implementation/CortexM3/vectors/tbench/Crf2Vrf
implementation/CortexM3/vectors/tbench/BuildNetlistMTI
implementation/CortexM3/vectors/tbench/ReplayNC
implementation/CortexM3/vectors/tbench/BuildNetlistVCS
implementation/CortexM3/vectors/tbench/verilog.vc
implementation/CortexM3Integration/
implementation/CortexM3Integration/vectors/
implementation/CortexM3Integration/vectors/crf/
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.ctrm
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_Instruction.capture.log.Z
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_Instruction.crf.Z
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_Instruction_netlist.replay.log.Z
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_Instruction_verilog.replay.log.Z
implementation/CortexM3Integration/vectors/tbench/
implementation/CortexM3Integration/vectors/tbench/VerilogCrf/
implementation/CortexM3Integration/vectors/tbench/VerilogCrf/Ctrm.pm
implementation/CortexM3Integration/vectors/tbench/BuildVerilogMTI
implementation/CortexM3Integration/vectors/tbench/CortexM3Integration_Replay_tb.v
implementation/CortexM3Integration/vectors/tbench/BuildNetlistNC
implementation/CortexM3Integration/vectors/tbench/BuildVerilogVCS
implementation/CortexM3Integration/vectors/tbench/ReplayMTI
implementation/CortexM3Integration/vectors/tbench/BuildVerilogNC
implementation/CortexM3Integration/vectors/tbench/ReplayVCS
implementation/CortexM3Integration/vectors/tbench/netlist.vc
implementation/CortexM3Integration/vectors/tbench/Crf2Vrf
implementation/CortexM3Integration/vectors/tbench/BuildNetlistMTI
implementation/CortexM3Integration/vectors/tbench/ReplayNC
implementation/CortexM3Integration/vectors/tbench/BuildNetlistVCS
implementation/CortexM3Integration/vectors/tbench/verilog.vc

AT425-VE-70002-r2p0-00rel0:

implementation/
implementation/CortexM3/
implementation/CortexM3/vectors/
implementation/CortexM3/vectors/crf/
implementation/CortexM3/vectors/crf/CortexM3.Portable_MaxSpeed.capture.log.Z
implementation/CortexM3/vectors/crf/CortexM3.Portable_MaxSpeed.crf.Z
implementation/CortexM3/vectors/crf/CortexM3.Portable_MaxSpeed_netlist.replay.log.Z
implementation/CortexM3/vectors/crf/CortexM3.Portable_MaxSpeed_verilog.replay.log.Z
implementation/CortexM3Integration/
implementation/CortexM3Integration/vectors/
implementation/CortexM3Integration/vectors/crf/
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_MaxSpeed.capture.log.Z
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_MaxSpeed.crf.Z
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_MaxSpeed_netlist.replay.log.Z
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_MaxSpeed_verilog.replay.log.Z

AT425-VE-70004-r2p0-00rel0:

implementation/
implementation/CortexM3/
implementation/CortexM3/vectors/
implementation/CortexM3/vectors/crf/
implementation/CortexM3/vectors/crf/CortexM3.Portable_TypPower.capture.log.Z
implementation/CortexM3/vectors/crf/CortexM3.Portable_TypPower.crf.Z
implementation/CortexM3/vectors/crf/CortexM3.Portable_TypPower_verilog.replay.log.Z
implementation/CortexM3/vectors/crf/CortexM3.Portable_TypPower_netlist.replay.log.Z
implementation/CortexM3Integration/
implementation/CortexM3Integration/vectors/
implementation/CortexM3Integration/vectors/crf/
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_TypPower.capture.log.Z
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_TypPower.crf.Z
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_TypPower_verilog.replay.log.Z
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_TypPower_netlist.replay.log.Z

AT425-VE-70023-r2p0-00rel0:

implementation/
implementation/CortexM3/
implementation/CortexM3/vectors/
implementation/CortexM3/vectors/crf/
implementation/CortexM3/vectors/crf/CortexM3.Portable_MaxPower.capture.log.Z
implementation/CortexM3/vectors/crf/CortexM3.Portable_MaxPower.crf.Z
implementation/CortexM3/vectors/crf/CortexM3.Portable_MaxPower_verilog.replay.log.Z
implementation/CortexM3/vectors/crf/CortexM3.Portable_MaxPower_netlist.replay.log.Z
implementation/CortexM3Integration/
implementation/CortexM3Integration/vectors/
implementation/CortexM3Integration/vectors/crf/
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_MaxPower.capture.log.Z
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_MaxPower.crf.Z
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_MaxPower_verilog.replay.log.Z
implementation/CortexM3Integration/vectors/crf/CortexM3Integration.Portable_MaxPower_netlist.replay.log.Z

gxliu08

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