025 always @ (posedge Clk or negedge Rst_n) 026 if(!Rst_n) begin 027 Rs232_Rx0 <= 1'b0; 028 Rs232_Rx1 <= 1'b0; 029 Rs232_Rx2 <= 1'b0; 030 Rs232_Rx3 <= 1'b0; 031 end 032 else begin 033 Rs232_Rx0 <= Rs232_Rx; 034 Rs232_Rx1 <= Rs232_Rx0; 035 Rs232_Rx2 <= Rs232_Rx1; 036 Rs232_Rx3 <= Rs232_Rx2; 037 end 038 039 wire neg_Rs232_Rx= Rs232_Rx3 & Rs232_Rx2 & ~Rs232_Rx1 & ~Rs232_Rx0; 040 041 assign Byte_En = neg_Rs232_Rx; 042 043 /*----------计数采样时钟--------------*/ 044 /*9倍波特率采样时钟,故一个完整的接收过程有90个波特率时钟*/ 045 reg[6:0]Sample_Clk_Cnt; 046 always @ (posedge Clk or negedge Rst_n) 047 if(!Rst_n) 048 Sample_Clk_Cnt <= 7'd0; 049 else if(Sample_Clk)begin 050 if(Sample_Clk_Cnt == 7'd89) 051 Sample_Clk_Cnt <= 7'd0; 052 else 053 Sample_Clk_Cnt <= Sample_Clk_Cnt + 1'b1; 054 end 055 else 056 Sample_Clk_Cnt <= Sample_Clk_Cnt; 057 058 reg [1:0]Start_Bit; /*起始位,这里虽然定义,但并未使用该位来判断接收数据的正确性,即默认接收都是成功的*/ 059 reg [1:0]Stop_Bit; /*停止位,这里虽然定义,但并未使用该位来判断接收数据的正确性,即默认接收都是成功的*/ 060 reg [1:0] Data_Tmp[7:0];/*此部分较为复杂,请参看说明文档中相关解释*/ 061 062 always @ (posedge Clk or negedge Rst_n) 063 if(!Rst_n)begin 064 Data_Tmp[0] <= 2'd0; 065 Data_Tmp[1] <= 2'd0; 066 Data_Tmp[2] <= 2'd0; 067 Data_Tmp[3] <= 2'd0; 068 Data_Tmp[4] <= 2'd0; 069 Data_Tmp[5] <= 2'd0; 070 Data_Tmp[6] <= 2'd0; 071 Data_Tmp[7] <= 2'd0; 072 Start_Bit <= 2'd0; 073 Stop_Bit <= 2'd0; 074 end 075 else if(Sample_Clk)begin 076 case(Sample_Clk_Cnt) 077 7'd0: 078 begin 079 Data_Tmp[0] <= 2'd0; 080 Data_Tmp[1] <= 2'd0; 081 Data_Tmp[2] <= 2'd0; 082 Data_Tmp[3] <= 2'd0; 083 Data_Tmp[4] <= 2'd0; 084 Data_Tmp[5] <= 2'd0; 085 Data_Tmp[6] <= 2'd0; 086 Data_Tmp[7] <= 2'd0; 087 Start_Bit <= 2'd0; 088 Stop_Bit <= 2'd0; 089 end 090 7'd3,7'd4,7'd5: Start_Bit <= Start_Bit + Rs232_Rx; 091 7'd12,7'd13,7'd14:Data_Tmp[0] <= Data_Tmp[0] + Rs232_Rx; 092 7'd21,7'd22,7'd23:Data_Tmp[1] <= Data_Tmp[1] + Rs232_Rx; 093 7'd30,7'd31,7'd32:Data_Tmp[2] <= Data_Tmp[2] + Rs232_Rx; 094 7'd39,7'd40,7'd41:Data_Tmp[3] <= Data_Tmp[3] + Rs232_Rx; 095 7'd48,7'd49,7'd50:Data_Tmp[4] <= Data_Tmp[4] + Rs232_Rx; 096 7'd57,7'd58,7'd59:Data_Tmp[5] <= Data_Tmp[5] + Rs232_Rx; 097 7'd66,7'd67,7'd68:Data_Tmp[6] <= Data_Tmp[6] + Rs232_Rx; 098 7'd75,7'd76,7'd77:Data_Tmp[7] <= Data_Tmp[7] + Rs232_Rx; 099 7'd84,7'd85,7'd86:Stop_Bit <= Stop_Bit + Rs232_Rx; 100 default:; 101 endcase 102 end 103 else ; |