430外设引脚配置问题

曾经in

430外设引脚配置问题 [复制链接]

英语底子差真是硬伤，不瞎搞了，来问问大伙这是fr59 SPI 例程的IO配置，为什么都用Input模式？



数据手册写了引脚功能，没找到详细配置信息，配置详细信息是写在哪里？？

强仔00001

你看看他的底层代码，我是直接配置寄存器的

曾经in

强仔00001 发表于 2015-2-8 12:34
你看看他的底层代码，我是直接配置寄存器的

用库和直接配置差不多，最终都是配置DIR和SEL。
烦恼的是不知道外设如何配置引脚模式写在什么文档里？

强仔00001

曾经in 发表于 2015-2-8 12:43
用库和直接配置差不多，最终都是配置DIR和SEL。
烦恼的是不知道外设如何配置引脚模式该在什么文档查看？

有个文档看的，很简单

曾经in

强仔00001 发表于 2015-2-8 12:45
有个文档看的，很简单

没找到呃呃呃呃，在哪里？数据手册还是用户指南？

曾经in

还是别的？？

曾经in

终于搞清楚了，用户指南22.3.3：
• The fourth pin is used as input to prevent conflicts with other masters (UCSTEM = 0).
• The fourth pin is used as output to generate a slave enable signal (UCSTEM = 1).

强仔00001

曾经in 发表于 2015-2-8 15:04
终于搞清楚了，用户指南22.3.3：
• The fourth pin is used as input to prevent conflicts with other masters (UCSTEM = 0).
• The fourth pin is used as output to generate a slave enable signal (UCSTEM = 1).

原来这样

曾经in

22.3 eUSCI Operation – SPI Mode
In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by
the master. An additional pin controlled by the master, UCxSTE, is provided to enable a device to receive
and transmit data.
Three or four signals are used for SPI data exchange:
• UCxSIMO – slave in, master out
Master mode: UCxSIMO is the data output line.
Slave mode: UCxSIMO is the data input line.
• UCxSOMI – slave out, master in
Master mode: UCxSOMI is the data input line.
Slave mode: UCxSOMI is the data output line.
• UCxCLK – eUSCI SPI clock
Master mode: UCxCLK is an output.
Slave mode: UCxCLK is an input.
• UCxSTE – slave transmit enable.