【Arrow SoC】系统参考设计用户手册

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【Arrow SoC】系统参考设计用户手册 [复制链接]

Attention: this is a copy of the GSRD User Manual. It has been modified to document how to use the Golden System Reference Design with the Arrow SoCKit.

• Getting Started Guides
• GSRD Overview
• Release Notes
• Release Contents
• Release Location
• Prerequisites
• Default Paths
• GHRD Overview
• HPS Boot Flow
• Development Flow Overview
• Detailed GSRD Build Flow
• Linux Documentation
  

Getting Started Guides

• Booting Linux Using Prebuilt SD Card Image
• Connecting to Board Web Server
• Connecting to Board Using SSH
• Running Sample Linux Applications
• Compiling the Hardware Design
• Generating and Compiling the Preloader
• Generating the Device Tree
• Compiling Linux
• Creating and Updating SD Card
• GSRD FPGA Programming
• Programming the FPGA with the Quartus II Programmer
• Using System Console
• Booting from FPGA
• Using Git Trees
• Booting from QSPI Flash
• Programming QSPI Flash
• Customizing HPS Clocks in Preloader
• Preloader and U-Boot Customization
  

GSRD Overview
[size=1em]The [size=1em]GSRD (Golden System Reference Design) provides a set of essential hardware and software system components that can be used as a starting point for various custom user designs.
The GSRD consists of:

• Arrow SoCKit Board
• Golden Hardware Reference Design (GHRD)
• Linux release
• Linux sample drivers
• Linux sample applications
• Web server running on target board
  

Release Notes
See Release Notes.
Release Contents
See Release Contents.Release Location
The GSRD release is located at the link above under Release Contents.Prerequisites
The following are required in order to be able to fully exercise the GSRD:

• Host PC running Linux (CentOS 6.3 or newer or Ubuntu 12.04LTS or newer preferred)
• Arrow SoCKit Board rev. B or later
• Altera SoC EDS v14.0 - available from http://www.altera.com/products/software/sfw-index.jsp
• Altera Quartus™ II v14.0 - available from http://www.altera.com/products/software/sfw-index.jsp
  

Default Paths

Throughout the documentation, the following default paths are assumed. Please update the commands accordingly if non-standard paths are used.

Default PathDescription
~/altera/14.0/embeddedSoC EDS installation path
~/altera/14.0/qprogrammerQuartus II Programmer installation path
~/altera/14.0/quartusQuartus II installation path
~/sockit_ghrdArrow SoCKit GHRD folder, extracted from sockit_ghrd_14.0.tar.gz

GHRD Overview
See GHRD Overview.
HPS Boot Flow
See HPS Boot Flow.
Development Flow Overview

The following picture presents a high level view of the development flow for projects based on the GSRD.

Detailed GSRD Build Flow
The following diagram illustrates the full build flow for the GSRD.

The following table presents the tools that are used in the build flow:ToolDescriptionPart of
Quartus IICreate, edit and compile FPGA hardware designs *ACDS
Device Tree GeneratorGenerate Device TreesSoC EDS
Device Tree CompilerConverts between Device Tree file formats
Preloader GeneratorGenerates Preloader source code based on hardware handoff information
ARM DS-5 AESoftware Development Suite
BitbakeYocto build utilityYocto Source Package
SD Card ScriptScript that creates the SD card image
The following table presents the input files that are part of the build process:FileDescription
Quartus ProjectFPGA Hardware Project source code
Board XMLFile describing the development board, used in creating the Device Tree
Clocking XMLFile describing the development board, used in creating the Device Tree
Yocto Source PackageYocto recipes and necessary packages and tools for building Linux
Web Server FilesAdditional files needed for the web server running on the board
The following table describes the rest of the items that are part of the build flow diagram:FileDescription
.sofSRAM Object File - FPGA programming file, resulted from compiling the FPGA hardware project
.rbfRaw Binary File - Compressed FPGA programing file
.dtsDevice Tree Source - used to describe the hardware for the Linux kernel
.dtbDevice Tree Binary - binary representation of the .dts
.sopcinfoSOPC Info File - containing a description of the hardware to be used by Device Tree Generator
.svdSystem View Description File - describes the hardware for the DS-5 debugger
HandoffFolder containing a description of the hardware to be used by the Preloader GeneratorNot all the people involved in a project need to deal with the full flow. For example:

• Board Designer: Typically works with the hardware engineer to decide the design of the custom board, pin muxing, and to update the Board XML file used by the Device Tree Generator.
• Hardware Engineer: Usually works only on the FPGA Quartus Project, and notifies the firmware engineer whenever the hardware files (.sof, .rbf, .sopcinfo, handoff folder) were changed. He also needs to notify the firmware engineer of any hardware interface changes.
• Firmware Engineer: Typically updates the Linux drivers according to the changes that were performed in hardware, recompiles the kernel if necessary. Re-generates the Device Tree when needed.
• Software Engineer: Develops the applications that run on top of the Linux OS. May need to change the software when new drivers are added.
  

Linux Documentation

• Linux BSP User Manual
• Yocto User Manual
• Device Tree Generator User Guide
  

lyzhangxiang

好多资料啊
altera 的资料总是那么多，针对广大用户，赞一个

xilinx的东西开源社区玩的多，基本上都是借助开源或者高校来推广

908508455a

不错嘛，不过为啥中文的好少啊

besk