【Arrow SoC】如何编译硬件系统

chenzhufly

【Arrow SoC】如何编译硬件系统 [复制链接]

 

• Overview
• Prerequisites
• Procedure
  • Open Quartus Project
  • Generate System in Qsys
  • Compile the Design in Quartus
    • Running Analysis & Synthesis
    • Running the Assembler
      
    
    
• Generated Files
• Converting .sof to .rbf
  

Overview
This page demonstrates how to compile the FPGA Hardware design that is delivered as part of the release.

The compilation will produce the following items:FileDescription
.sofSRAM Object File - FPGA programming file, resulted from compiling the FPGA hardware project
.sopcinfoSOPC Info File - containing a description of the hardware to be used by Device Tree Generator
.svdSystem View Description File - describes the hardware for the DS-5 debugger
HandoffFolder containing a description of the hardware to be used by the Preloader Generator
Prerequisites
The following items are required:

• Host PC running Linux (CentOS 6.3 or newer or Ubuntu 12.04LTS or newer preferred)
• Altera Quartus™ II v14.0 - available from http://www.altera.com/products/software/sfw-index.jsp
• GHRD Archive from sockit_ghrd_14.0.tar.gz
  

Procedure

[size=1em]The procedure described below uses the Cyclone V GHRD. The procedure for Arria V GHRD is similar, with only the file names being changed:

FileCyclone V
GHRD Archivesockit_ghrd_14.0.tar.gz
Quartus Projectsockit_ghrd/soc_system.qpf
Qsys Filesockit_ghrd/soc_system.qsys
Programming Filesockit_ghrd/output_files/soc_system.sofOpen Quartus Project
1. Retrieve and the archive file sockit_ghrd_14.0.tar.gz containing the hardware design and save it in the home folder. The file is available at sockit_ghrd_14.0.tar.gz.
2. Extract the files from the archive$ cd ~$ tar xzf sockit_ghrd_14.0.tar.gz
3. Make all the files writable (optional)$ chmod 777 -R ~sockit_ghrd
4. Start Quartus tool by double clicking the icon on the desktop, or by running it from the command line:$ ~/altera/14.0/quartus/bin/quartus --64bit
5. In Quartus, go to File -> Open Project ..., browse to the file sockit_ghrd/soc_system.qpf and click Open.

[size=1em]6. Quartus will load the project.

Generate System in Qsys
7. In Quartus, go to Tools -> Qsys to start the Qsys tool

8. Qsys tool will start and ask you to open a Qsys file. Select sockit_ghrd/soc_system.qsys and click Open.

[size=1em]9. Qsys will load the file

10. In Qsys, select Generate -≫ Generate this will open the Generate dialogue box.

11. In the Generate dialogue box, click the Generate button.

[size=1em]12. A message will be displayed when the generation is complete (may take a few minutes depending on host machine speed)

13. Click Close button in the Generation window to close it.
14. In Qsys, go to File -> Exit to close Qsys.

Compile the Design in Quartus
Running Analysis & Synthesis
15. In Quartus, in the Tasks panel change the flow from RTL Simulation to Compilation.

16. In the Tasks panel, right click Analysis and Synthesis and select Start.

[size=1em]17. After a few minutes (depending on host machine speed) the Analysis & Synthesis will finish and a message will be displayed.

Running the Assembler
21. In the Tasks panel, select Assembler, right click it and select Start.

[size=1em]22. After the assembly phase is completed, a notification message will be displayed.

Generated Files
This section presents the name and location of the files resulted from compiling the hardware design.FileDescription
sockit_ghrd/output_files/soc_system.sofSRAM Object File - for programming FPGA
sockit_ghrd/soc_system.sopcinfoSOPC Info File - Used by Device Tree Generator
sockit_ghrd/soc_system/synthesis/soc_system_hps_0_hps.svdSystem View File - Used by ARM DS-5 AE
sockit_ghrd/hps_isw_handoffHandoff folder - Used by Preloader GeneratorConverting .sof to .rbf

[size=1em]The SOF (SRAM Object File) file can use used to program the FPGA from the Quartus Programmer tool.

[size=1em]However, for the purpose of programming the FPGA from software, the SOF file needs to be converted to a RBF (Raw Binary File) format.

[size=1em]Several different options are available for converting the file:

A. Using the command line tools from Quartus Programmer (installed by default with the SoC EDS or installed standalone) or from Quartus. $ ~/altera/14.0/quartus/bin/quartus_cpf -c \
  sockit_ghrd/output_files/soc_system.sof  \
  sockit_ghrd/output_files/soc_system.rbf  $ ~/altera/14.0/qprogrammer/bin/quartus_cpf -c \
  sockit_ghrd/output_files/soc_system.sof  \
  sockit_ghrd/output_files/soc_system.rbf
B. Using the GUI converter, callable from either Quartus Programmer or Quartus by selecting the menu File -> Convert Programming Files.

• Select the Programming File Type to be Raw Binary File (.rbf)
• Select the Mode to be Fast Passive Parallel X8 or 16
• Click on the SOF Data then click Add File and browse to the soc_system.sof file
• Edit the desired name of the output file to be soc_system.rbf
• Click the Generate button
  

lelee007

点赞！

尽职尽责的好斑竹，这个是你自己操作过程的截图？

我 都是直接把arrow给的lab文档整个直接上传上来，自己 只对着操作了一下，惭愧惭愧

scsi

不容易呀