ISE调用modelsim作时序仿真时，出现的问题

lihaie

ISE调用modelsim作时序仿真时，出现的问题 [复制链接]

** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:13394 ps, negedge I &&& (in_clk_enable1 != 0):13435 ps, 169 ps );
#    Time: 13435 ps  Iteration: 1  Instance: /oneam_tb/uut/\am1/blk00000641
# ** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:13394 ps, negedge I &&& (in_clk_enable1 != 0):13442 ps, 169 ps );
#    Time: 13442 ps  Iteration: 0  Instance: /oneam_tb/uut/\am1/blk00000640
# ** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(103): $hold( posedge CLK:13416 ps, posedge I &&& (in_clk_enable1 != 0):13452 ps, 169 ps );
#    Time: 13452 ps  Iteration: 0  Instance: /oneam_tb/uut/\am1/blk00000655
# ** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:13400 ps, negedge I &&& (in_clk_enable1 != 0):13478 ps, 169 ps );
#    Time: 13478 ps  Iteration: 0  Instance: /oneam_tb/uut/\am1/blk00000643
# ** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:13394 ps, negedge I &&& (in_clk_enable1 != 0):13495 ps, 169 ps );
#    Time: 13495 ps  Iteration: 0  Instance: /oneam_tb/uut/\am1/blk00000642
# ** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:13400 ps, negedge I &&& (in_clk_enable1 != 0):13526 ps, 169 ps );
#    Time: 13526 ps  Iteration: 0  Instance: /oneam_tb/uut/\am1/blk00000645
# ** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:13400 ps, negedge I &&& (in_clk_enable1 != 0):13533 ps, 169 ps );
#    Time: 13533 ps  Iteration: 0  Instance: /oneam_tb/uut/\am1/blk00000644
# ** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(103): $hold( posedge CLK:13413 ps, posedge I &&& (in_clk_enable1 != 0):13563 ps, 169 ps );
#    Time: 13563 ps  Iteration: 0  Instance: /oneam_tb/uut/\am1/blk00000652
# ** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:13405 ps, negedge I &&& (in_clk_enable1 != 0):13569 ps, 169 ps );
#    Time: 13569 ps  Iteration: 0  Instance: /oneam_tb/uut/\am1/blk00000647
# ** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(103): $hold( posedge CLK:13413 ps, posedge I &&& (in_clk_enable1 != 0):13577 ps, 169 ps );
#    Time: 13577 ps  Iteration: 0  Instance: /oneam_tb/uut/\am1/blk00000651
# ** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(103): $hold( posedge CLK:15423 ps, posedge I &&& (in_clk_enable1 != 0):15462 ps, 169 ps );
#    Time: 15462 ps  Iteration: 0  Instance: /oneam_tb/uut/\am1/blk00000756
# ** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(103): $hold( posedge CLK:15423 ps, posedge I &&& (in_clk_enable1 != 0):15510 ps, 169 ps );
#    Time: 15510 ps  Iteration: 0  Instance: /oneam_tb/uut/\am1/blk00000754
# ** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(103): $hold( posedge CLK:15435 ps, posedge I &&& (in_clk_enable1 != 0):15544 ps, 169 ps );
#    Time: 15544 ps  Iteration: 0  Instance: /oneam_tb/uut/\am1/blk00000763
# ** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:17423 ps, negedge I &&& (in_clk_enable1 != 0):17462 ps, 169 ps );
#    Time: 17462 ps  Iteration: 0  Instance: /oneam_tb/uut/\am1/blk00000756
# ** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:17423 ps, negedge I &&& (in_clk_enable1 != 0):17510 ps, 169 ps );
#    Time: 17510 ps  Iteration: 0  Instance: /oneam_tb/uut/\am1/blk00000754
# ** Error: E:/software/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:17435 ps, negedge I &&& (in_clk_enable1 != 0):17544 ps, 169 ps );
#    Time: 17544 ps  Iteration: 0  Instance: /oneam_tb/uut/\am1/blk00000763

gh131413

这是作什么的节奏，编译错误……

lihaie

gh131413 发表于 2014-4-23 09:56
这是作什么的节奏，编译错误……

这是ISE调用modelsim仿真时出现的错误

lihaie

问题已解决，在于testbench的仿真时钟有问题

祁东杰

lihaie 发表于 2014-4-23 14:20
问题已解决，在于testbench的仿真时钟有问题

能问一下是时钟是怎么出问题的吗？最近也遇到这个问题，各种搞不定。

franky1006

太麻烦……

lihaie

祁东杰 发表于 2014-5-6 22:24
能问一下是时钟是怎么出问题的吗？最近也遇到这个问题，各种搞不定。

是testbench中的always # 1 clk=~clk;设计出的问题，这样设计的话，时钟频率是1000/2=500Mhz，如果改为 # 4的话，时钟频率就变为1000/8=125mhz了，这就是我出现ERROR的原因，不知道对你有没有帮助。