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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity debounce_FSM is
- generic (fclk : integer :=50000000);
- port(
- n_rst : in std_logic;
- clk : in std_logic;
- key_in : in std_logic; --key is valid by low
- pulse : out std_logic --output single pulse
- );
- end debounce_FSM;
- architecture rtl of debounce_FSM is
- type m_state is(
- idle,
- delay,
- output,
- key_up
- );
- signal cs,ns: m_state;
- signal key_reg : std_logic;
- constant n : integer :=fclk/100; --100Hz,means to delay 10 ms
- signal delay_cnt : integer range 0 to n-1;
- begin
- --three section FSM
- --timing sequence part of FSM
- process(n_rst,clk)
- begin
- if(n_rst='0')then
- cs<=idle;
- elsif(clk'event and clk='1')then
- cs<=ns;
- end if;
- end process;
- --combination part of FSM
- process(cs,key_in,delay_cnt)
- begin
- case (cs) is
- when idle => if(key_in='0')then
- ns<=delay; --when key is down
- else
- ns<=idle;
- end if;
- when delay => if(delay_cnt=n-1)then
- ns<=output;
- else
- ns<=delay;
- end if;
- when output => ns<=key_up;
- when key_up => if(key_in='1')then --waiting key being up
- ns<=idle;
- else
- ns<=key_up;
- end if;
- when others => ns<=idle;
- end case;
- end process;
-
- --register output part of FSM
- process(n_rst,clk)
- begin
- if(n_rst='0')then
- key_reg <='0';
- delay_cnt<=0;
- elsif(clk'event and clk='1')then
- case (ns) is
- when idle => key_reg <='0';delay_cnt<=0;
- when delay => key_reg <='0';delay_cnt<=delay_cnt+1;
- when output => if(key_in='0')then
- key_reg <='1';
- else
- key_reg <='0';
- end if;
- delay_cnt<=delay_cnt;
- when key_up => key_reg <='0';delay_cnt<=0;
- when others => key_reg <='0';delay_cnt<=0;
- end case;
- end if;
- end process;
- pulse<=key_reg;
-
- end rtl;
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